1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 23 #define _REO_UPDATE_RX_REO_QUEUE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_cmd_header.h" 28 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 29 30 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 31 32 struct reo_update_rx_reo_queue { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct uniform_reo_cmd_header cmd_header; 35 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 36 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 37 update_receive_queue_number : 1, 38 update_vld : 1, 39 update_associated_link_descriptor_counter : 1, 40 update_disable_duplicate_detection : 1, 41 update_soft_reorder_enable : 1, 42 update_ac : 1, 43 update_bar : 1, 44 update_rty : 1, 45 update_chk_2k_mode : 1, 46 update_oor_mode : 1, 47 update_ba_window_size : 1, 48 update_pn_check_needed : 1, 49 update_pn_shall_be_even : 1, 50 update_pn_shall_be_uneven : 1, 51 update_pn_handling_enable : 1, 52 update_pn_size : 1, 53 update_ignore_ampdu_flag : 1, 54 update_svld : 1, 55 update_ssn : 1, 56 update_seq_2k_error_detected_flag : 1, 57 update_pn_error_detected_flag : 1, 58 update_pn_valid : 1, 59 update_pn : 1, 60 clear_stat_counters : 1; 61 uint32_t receive_queue_number : 16, 62 vld : 1, 63 associated_link_descriptor_counter : 2, 64 disable_duplicate_detection : 1, 65 soft_reorder_enable : 1, 66 ac : 2, 67 bar : 1, 68 rty : 1, 69 chk_2k_mode : 1, 70 oor_mode : 1, 71 pn_check_needed : 1, 72 pn_shall_be_even : 1, 73 pn_shall_be_uneven : 1, 74 pn_handling_enable : 1, 75 ignore_ampdu_flag : 1; 76 uint32_t ba_window_size : 10, 77 pn_size : 2, 78 svld : 1, 79 ssn : 12, 80 seq_2k_error_detected_flag : 1, 81 pn_error_detected_flag : 1, 82 pn_valid : 1, 83 flush_from_cache : 1, 84 reserved_4a : 3; 85 uint32_t pn_31_0 : 32; 86 uint32_t pn_63_32 : 32; 87 uint32_t pn_95_64 : 32; 88 uint32_t pn_127_96 : 32; 89 uint32_t tlv64_padding : 32; 90 #else 91 struct uniform_reo_cmd_header cmd_header; 92 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 93 uint32_t clear_stat_counters : 1, 94 update_pn : 1, 95 update_pn_valid : 1, 96 update_pn_error_detected_flag : 1, 97 update_seq_2k_error_detected_flag : 1, 98 update_ssn : 1, 99 update_svld : 1, 100 update_ignore_ampdu_flag : 1, 101 update_pn_size : 1, 102 update_pn_handling_enable : 1, 103 update_pn_shall_be_uneven : 1, 104 update_pn_shall_be_even : 1, 105 update_pn_check_needed : 1, 106 update_ba_window_size : 1, 107 update_oor_mode : 1, 108 update_chk_2k_mode : 1, 109 update_rty : 1, 110 update_bar : 1, 111 update_ac : 1, 112 update_soft_reorder_enable : 1, 113 update_disable_duplicate_detection : 1, 114 update_associated_link_descriptor_counter : 1, 115 update_vld : 1, 116 update_receive_queue_number : 1, 117 rx_reo_queue_desc_addr_39_32 : 8; 118 uint32_t ignore_ampdu_flag : 1, 119 pn_handling_enable : 1, 120 pn_shall_be_uneven : 1, 121 pn_shall_be_even : 1, 122 pn_check_needed : 1, 123 oor_mode : 1, 124 chk_2k_mode : 1, 125 rty : 1, 126 bar : 1, 127 ac : 2, 128 soft_reorder_enable : 1, 129 disable_duplicate_detection : 1, 130 associated_link_descriptor_counter : 2, 131 vld : 1, 132 receive_queue_number : 16; 133 uint32_t reserved_4a : 3, 134 flush_from_cache : 1, 135 pn_valid : 1, 136 pn_error_detected_flag : 1, 137 seq_2k_error_detected_flag : 1, 138 ssn : 12, 139 svld : 1, 140 pn_size : 2, 141 ba_window_size : 10; 142 uint32_t pn_31_0 : 32; 143 uint32_t pn_63_32 : 32; 144 uint32_t pn_95_64 : 32; 145 uint32_t pn_127_96 : 32; 146 uint32_t tlv64_padding : 32; 147 #endif 148 }; 149 150 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 151 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 152 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 153 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 154 155 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 156 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 157 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 158 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 159 160 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 161 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 162 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 163 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 164 165 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 166 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 167 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 168 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 169 170 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 171 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 172 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 173 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 174 175 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 176 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 177 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 178 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 179 180 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 181 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 182 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 183 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 184 185 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 186 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 187 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 188 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 189 190 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 191 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 192 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 193 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 194 195 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 196 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 197 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 198 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 199 200 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 201 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 202 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 203 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 204 205 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 206 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 207 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 208 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 209 210 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 211 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 212 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 213 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 214 215 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 216 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 217 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 218 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 219 220 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 221 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 222 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 223 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 224 225 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 226 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 227 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 228 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 229 230 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 231 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 232 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 233 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 234 235 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 236 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 237 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 238 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 239 240 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 241 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 242 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 243 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 244 245 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 246 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 247 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 248 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 249 250 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 251 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 252 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 253 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 254 255 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 256 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 257 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 258 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 259 260 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 261 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 262 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 263 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 264 265 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 266 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 267 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 268 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 269 270 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 271 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 272 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 273 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 274 275 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 276 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 277 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 278 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 279 280 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 281 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 282 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 283 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 284 285 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 286 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 287 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 288 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 289 290 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 291 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 292 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 293 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 294 295 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 296 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 297 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 298 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 299 300 #define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 301 #define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 302 #define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 303 #define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 304 305 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 306 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 307 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 308 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 309 310 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 311 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 312 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 313 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 314 315 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 316 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 317 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 318 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 319 320 #define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 321 #define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 322 #define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 323 #define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 324 325 #define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 326 #define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 327 #define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 328 #define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 329 330 #define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 331 #define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 332 #define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 333 #define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 334 335 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 336 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 337 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 338 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 339 340 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 341 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 342 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 343 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 344 345 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 346 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 347 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 348 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 349 350 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 351 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 352 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 353 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 354 355 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 356 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 357 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 358 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 359 360 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 361 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 362 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 363 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 364 365 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 366 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 367 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 368 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 369 370 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 371 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 372 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 373 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff 374 375 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 376 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 377 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 378 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 379 380 #define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 381 #define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 382 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 383 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 384 385 #define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 386 #define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 387 #define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 388 #define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 389 390 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 391 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 392 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 393 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 394 395 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 396 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 397 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 398 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 399 400 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 401 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 402 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 403 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 404 405 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 406 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 407 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 408 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 409 410 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 411 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 412 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 413 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 414 415 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 416 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 417 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 418 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 419 420 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 421 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 422 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 423 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff 424 425 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 426 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 427 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 428 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 429 430 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 431 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 432 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 433 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff 434 435 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 436 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 437 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 438 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 439 440 #endif 441