1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _RESPONSE_END_STATUS_H_ 21 #define _RESPONSE_END_STATUS_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "phytx_abort_request_info.h" 26 #define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 27 28 #define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 29 30 struct response_end_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t coex_bt_tx_while_wlan_tx : 1, 33 coex_wan_tx_while_wlan_tx : 1, 34 coex_wlan_tx_while_wlan_tx : 1, 35 global_data_underflow_warning : 1, 36 response_transmit_status : 4, 37 phytx_pkt_end_info_valid : 1, 38 phytx_abort_request_info_valid : 1, 39 generated_response : 3, 40 mba_user_count : 7, 41 mba_fake_bitmap_count : 7, 42 coex_based_tx_bw : 3, 43 trig_response_related : 1, 44 dpdtrain_done : 1; 45 struct phytx_abort_request_info phytx_abort_request_info_details; 46 uint16_t cbf_segment_request_mask : 8, 47 cbf_segment_sent_mask : 8; 48 uint32_t underflow_mpdu_count : 9, 49 data_underflow_warning : 2, 50 phy_tx_gain_setting : 8, 51 timing_status : 2, 52 only_null_delim_sent : 1, 53 brp_info_valid : 1, 54 reserved_2a : 9; 55 uint32_t mu_response_bitmap_31_0 : 32; 56 uint32_t mu_response_bitmap_36_32 : 5, 57 reserved_4a : 11, 58 transmit_delay : 16; 59 uint32_t start_of_frame_timestamp_15_0 : 16, 60 start_of_frame_timestamp_31_16 : 16; 61 uint32_t end_of_frame_timestamp_15_0 : 16, 62 end_of_frame_timestamp_31_16 : 16; 63 uint32_t tx_group_delay : 12, 64 reserved_7a : 4, 65 tpc_dbg_info_cmn_15_0 : 16; 66 uint32_t tpc_dbg_info_31_16 : 16, 67 tpc_dbg_info_47_32 : 16; 68 uint32_t tpc_dbg_info_chn1_15_0 : 16, 69 tpc_dbg_info_chn1_31_16 : 16; 70 uint32_t tpc_dbg_info_chn1_47_32 : 16, 71 tpc_dbg_info_chn1_63_48 : 16; 72 uint32_t tpc_dbg_info_chn1_79_64 : 16, 73 tpc_dbg_info_chn2_15_0 : 16; 74 uint32_t tpc_dbg_info_chn2_31_16 : 16, 75 tpc_dbg_info_chn2_47_32 : 16; 76 uint32_t tpc_dbg_info_chn2_63_48 : 16, 77 tpc_dbg_info_chn2_79_64 : 16; 78 uint32_t phytx_tx_end_sw_info_15_0 : 16, 79 phytx_tx_end_sw_info_31_16 : 16; 80 uint32_t phytx_tx_end_sw_info_47_32 : 16, 81 phytx_tx_end_sw_info_63_48 : 16; 82 uint32_t addr1_31_0 : 32; 83 uint32_t addr1_47_32 : 16, 84 addr2_15_0 : 16; 85 uint32_t addr2_47_16 : 32; 86 uint32_t addr3_31_0 : 32; 87 uint32_t addr3_47_32 : 16, 88 __reserved_g_0005 : 1, 89 secure : 1, 90 __reserved_g_0005_ftm_frame_sent : 1, 91 reserved_20a : 13; 92 uint32_t tlv64_padding : 32; 93 #else 94 uint32_t dpdtrain_done : 1, 95 trig_response_related : 1, 96 coex_based_tx_bw : 3, 97 mba_fake_bitmap_count : 7, 98 mba_user_count : 7, 99 generated_response : 3, 100 phytx_abort_request_info_valid : 1, 101 phytx_pkt_end_info_valid : 1, 102 response_transmit_status : 4, 103 global_data_underflow_warning : 1, 104 coex_wlan_tx_while_wlan_tx : 1, 105 coex_wan_tx_while_wlan_tx : 1, 106 coex_bt_tx_while_wlan_tx : 1; 107 uint32_t cbf_segment_sent_mask : 8, 108 cbf_segment_request_mask : 8; 109 struct phytx_abort_request_info phytx_abort_request_info_details; 110 uint32_t reserved_2a : 9, 111 brp_info_valid : 1, 112 only_null_delim_sent : 1, 113 timing_status : 2, 114 phy_tx_gain_setting : 8, 115 data_underflow_warning : 2, 116 underflow_mpdu_count : 9; 117 uint32_t mu_response_bitmap_31_0 : 32; 118 uint32_t transmit_delay : 16, 119 reserved_4a : 11, 120 mu_response_bitmap_36_32 : 5; 121 uint32_t start_of_frame_timestamp_31_16 : 16, 122 start_of_frame_timestamp_15_0 : 16; 123 uint32_t end_of_frame_timestamp_31_16 : 16, 124 end_of_frame_timestamp_15_0 : 16; 125 uint32_t tpc_dbg_info_cmn_15_0 : 16, 126 reserved_7a : 4, 127 tx_group_delay : 12; 128 uint32_t tpc_dbg_info_47_32 : 16, 129 tpc_dbg_info_31_16 : 16; 130 uint32_t tpc_dbg_info_chn1_31_16 : 16, 131 tpc_dbg_info_chn1_15_0 : 16; 132 uint32_t tpc_dbg_info_chn1_63_48 : 16, 133 tpc_dbg_info_chn1_47_32 : 16; 134 uint32_t tpc_dbg_info_chn2_15_0 : 16, 135 tpc_dbg_info_chn1_79_64 : 16; 136 uint32_t tpc_dbg_info_chn2_47_32 : 16, 137 tpc_dbg_info_chn2_31_16 : 16; 138 uint32_t tpc_dbg_info_chn2_79_64 : 16, 139 tpc_dbg_info_chn2_63_48 : 16; 140 uint32_t phytx_tx_end_sw_info_31_16 : 16, 141 phytx_tx_end_sw_info_15_0 : 16; 142 uint32_t phytx_tx_end_sw_info_63_48 : 16, 143 phytx_tx_end_sw_info_47_32 : 16; 144 uint32_t addr1_31_0 : 32; 145 uint32_t addr2_15_0 : 16, 146 addr1_47_32 : 16; 147 uint32_t addr2_47_16 : 32; 148 uint32_t addr3_31_0 : 32; 149 uint32_t reserved_20a : 13, 150 __reserved_g_0005_ftm_frame_sent : 1, 151 secure : 1, 152 __reserved_g_0005 : 1, 153 addr3_47_32 : 16; 154 uint32_t tlv64_padding : 32; 155 #endif 156 }; 157 158 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 159 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 160 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 161 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 162 163 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 164 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 165 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 166 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 167 168 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 169 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 170 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 171 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 172 173 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 174 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 175 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 176 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 177 178 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 179 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 180 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 181 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 182 183 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 184 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 185 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 186 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 187 188 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 189 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 190 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 191 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 192 193 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 194 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 195 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 196 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 197 198 #define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 199 #define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 200 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 201 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 202 203 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 204 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 205 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 206 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 207 208 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 209 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 210 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 211 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 212 213 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 214 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 215 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 216 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 217 218 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 219 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 220 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 221 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 222 223 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 224 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 225 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 226 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 227 228 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 229 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 230 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 231 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 232 233 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 234 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 235 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 236 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 237 238 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 239 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 240 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 241 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 242 243 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 244 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 245 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 246 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 247 248 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 249 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 250 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 251 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 252 253 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 254 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 255 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 256 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 257 258 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 259 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 260 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 261 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 262 263 #define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 264 #define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 265 #define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 266 #define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 267 268 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 269 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 270 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 271 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 272 273 #define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 274 #define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 275 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 276 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 277 278 #define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 279 #define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 280 #define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 281 #define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 282 283 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 284 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 285 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 286 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 287 288 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 289 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 290 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 291 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f 292 293 #define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 294 #define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 295 #define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 296 #define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 297 298 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 299 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 300 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 301 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 302 303 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 304 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 305 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 306 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 307 308 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 309 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 310 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 311 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 312 313 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 314 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 315 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 316 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 317 318 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 319 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 320 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 321 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 322 323 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 324 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 325 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 326 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 327 328 #define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 329 #define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 330 #define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 331 #define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 332 333 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 334 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 335 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 336 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 337 338 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 339 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 340 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 341 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff 342 343 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 344 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 345 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 346 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 347 348 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 349 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 350 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 351 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 352 353 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 354 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 355 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 356 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 357 358 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 359 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 360 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 361 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 362 363 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 364 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 365 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 366 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 367 368 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 369 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 370 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 371 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 372 373 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 374 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 375 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 376 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 377 378 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 379 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 380 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 381 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 382 383 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 384 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 385 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 386 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 387 388 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 389 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 390 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 391 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 392 393 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 394 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 395 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 396 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 397 398 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 399 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 400 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 401 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 402 403 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 404 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 405 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 406 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 407 408 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 409 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 410 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 411 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 412 413 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 414 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 415 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 416 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 417 418 #define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 419 #define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 420 #define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 421 #define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff 422 423 #define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 424 #define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 425 #define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 426 #define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 427 428 #define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 429 #define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 430 #define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 431 #define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 432 433 #define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 434 #define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 435 #define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 436 #define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff 437 438 #define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 439 #define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 440 #define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 441 #define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 442 443 #define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 444 #define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 445 #define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 446 #define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff 447 448 #define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 449 #define RESPONSE_END_STATUS_SECURE_LSB 17 450 #define RESPONSE_END_STATUS_SECURE_MSB 17 451 #define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 452 453 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 454 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 455 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 456 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 457 458 #define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 459 #define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 460 #define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 461 #define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 462 463 #define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 464 #define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 465 #define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 466 #define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 467 468 #endif 469