1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _RESPONSE_START_STATUS_H_ 21 #define _RESPONSE_START_STATUS_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 26 27 #define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 28 29 struct response_start_status { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t generated_response : 3, 32 __reserved_g_0012 : 2, 33 trig_response_related : 1, 34 response_sta_count : 7, 35 reserved : 19; 36 uint32_t phy_ppdu_id : 16, 37 sw_peer_id : 16; 38 #else 39 uint32_t reserved : 19, 40 response_sta_count : 7, 41 trig_response_related : 1, 42 __reserved_g_0012 : 2, 43 generated_response : 3; 44 uint32_t sw_peer_id : 16, 45 phy_ppdu_id : 16; 46 #endif 47 }; 48 49 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 50 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 51 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 52 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 53 54 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 55 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 56 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 57 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 58 59 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 60 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 61 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 62 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 63 64 #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 65 #define RESPONSE_START_STATUS_RESERVED_LSB 13 66 #define RESPONSE_START_STATUS_RESERVED_MSB 31 67 #define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 68 69 #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 70 #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 71 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 72 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 73 74 #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 75 #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 76 #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 77 #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 78 79 #endif 80