1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_ATTENTION_H_ 23 #define _RX_ATTENTION_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_ATTENTION 4 28 29 #define NUM_OF_QWORDS_RX_ATTENTION 2 30 31 struct rx_attention { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 uint32_t rxpcu_mpdu_filter_in_category : 2, 34 sw_frame_group_id : 7, 35 reserved_0 : 7, 36 phy_ppdu_id : 16; 37 uint32_t first_mpdu : 1, 38 reserved_1a : 1, 39 mcast_bcast : 1, 40 ast_index_not_found : 1, 41 ast_index_timeout : 1, 42 power_mgmt : 1, 43 non_qos : 1, 44 null_data : 1, 45 mgmt_type : 1, 46 ctrl_type : 1, 47 more_data : 1, 48 eosp : 1, 49 a_msdu_error : 1, 50 fragment_flag : 1, 51 order : 1, 52 cce_match : 1, 53 overflow_err : 1, 54 msdu_length_err : 1, 55 tcp_udp_chksum_fail : 1, 56 ip_chksum_fail : 1, 57 sa_idx_invalid : 1, 58 da_idx_invalid : 1, 59 reserved_1b : 1, 60 rx_in_tx_decrypt_byp : 1, 61 encrypt_required : 1, 62 directed : 1, 63 buffer_fragment : 1, 64 mpdu_length_err : 1, 65 tkip_mic_err : 1, 66 decrypt_err : 1, 67 unencrypted_frame_err : 1, 68 fcs_err : 1; 69 uint32_t flow_idx_timeout : 1, 70 flow_idx_invalid : 1, 71 wifi_parser_error : 1, 72 amsdu_parser_error : 1, 73 sa_idx_timeout : 1, 74 da_idx_timeout : 1, 75 msdu_limit_error : 1, 76 da_is_valid : 1, 77 da_is_mcbc : 1, 78 sa_is_valid : 1, 79 decrypt_status_code : 3, 80 rx_bitmap_not_updated : 1, 81 reserved_2 : 17, 82 msdu_done : 1; 83 uint32_t tlv64_padding : 32; 84 #else 85 uint32_t phy_ppdu_id : 16, 86 reserved_0 : 7, 87 sw_frame_group_id : 7, 88 rxpcu_mpdu_filter_in_category : 2; 89 uint32_t fcs_err : 1, 90 unencrypted_frame_err : 1, 91 decrypt_err : 1, 92 tkip_mic_err : 1, 93 mpdu_length_err : 1, 94 buffer_fragment : 1, 95 directed : 1, 96 encrypt_required : 1, 97 rx_in_tx_decrypt_byp : 1, 98 reserved_1b : 1, 99 da_idx_invalid : 1, 100 sa_idx_invalid : 1, 101 ip_chksum_fail : 1, 102 tcp_udp_chksum_fail : 1, 103 msdu_length_err : 1, 104 overflow_err : 1, 105 cce_match : 1, 106 order : 1, 107 fragment_flag : 1, 108 a_msdu_error : 1, 109 eosp : 1, 110 more_data : 1, 111 ctrl_type : 1, 112 mgmt_type : 1, 113 null_data : 1, 114 non_qos : 1, 115 power_mgmt : 1, 116 ast_index_timeout : 1, 117 ast_index_not_found : 1, 118 mcast_bcast : 1, 119 reserved_1a : 1, 120 first_mpdu : 1; 121 uint32_t msdu_done : 1, 122 reserved_2 : 17, 123 rx_bitmap_not_updated : 1, 124 decrypt_status_code : 3, 125 sa_is_valid : 1, 126 da_is_mcbc : 1, 127 da_is_valid : 1, 128 msdu_limit_error : 1, 129 da_idx_timeout : 1, 130 sa_idx_timeout : 1, 131 amsdu_parser_error : 1, 132 wifi_parser_error : 1, 133 flow_idx_invalid : 1, 134 flow_idx_timeout : 1; 135 uint32_t tlv64_padding : 32; 136 #endif 137 }; 138 139 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 140 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 141 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 142 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 143 144 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 145 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 146 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 147 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 148 149 #define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 150 #define RX_ATTENTION_RESERVED_0_LSB 9 151 #define RX_ATTENTION_RESERVED_0_MSB 15 152 #define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 153 154 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 155 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 156 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 157 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 158 159 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 160 #define RX_ATTENTION_FIRST_MPDU_LSB 32 161 #define RX_ATTENTION_FIRST_MPDU_MSB 32 162 #define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 163 164 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 165 #define RX_ATTENTION_RESERVED_1A_LSB 33 166 #define RX_ATTENTION_RESERVED_1A_MSB 33 167 #define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 168 169 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 170 #define RX_ATTENTION_MCAST_BCAST_LSB 34 171 #define RX_ATTENTION_MCAST_BCAST_MSB 34 172 #define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 173 174 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 175 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 176 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 177 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 178 179 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 180 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 181 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 182 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 183 184 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 185 #define RX_ATTENTION_POWER_MGMT_LSB 37 186 #define RX_ATTENTION_POWER_MGMT_MSB 37 187 #define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 188 189 #define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 190 #define RX_ATTENTION_NON_QOS_LSB 38 191 #define RX_ATTENTION_NON_QOS_MSB 38 192 #define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 193 194 #define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 195 #define RX_ATTENTION_NULL_DATA_LSB 39 196 #define RX_ATTENTION_NULL_DATA_MSB 39 197 #define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 198 199 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 200 #define RX_ATTENTION_MGMT_TYPE_LSB 40 201 #define RX_ATTENTION_MGMT_TYPE_MSB 40 202 #define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 203 204 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 205 #define RX_ATTENTION_CTRL_TYPE_LSB 41 206 #define RX_ATTENTION_CTRL_TYPE_MSB 41 207 #define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 208 209 #define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 210 #define RX_ATTENTION_MORE_DATA_LSB 42 211 #define RX_ATTENTION_MORE_DATA_MSB 42 212 #define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 213 214 #define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 215 #define RX_ATTENTION_EOSP_LSB 43 216 #define RX_ATTENTION_EOSP_MSB 43 217 #define RX_ATTENTION_EOSP_MASK 0x0000080000000000 218 219 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 220 #define RX_ATTENTION_A_MSDU_ERROR_LSB 44 221 #define RX_ATTENTION_A_MSDU_ERROR_MSB 44 222 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 223 224 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 225 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 226 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 227 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 228 229 #define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 230 #define RX_ATTENTION_ORDER_LSB 46 231 #define RX_ATTENTION_ORDER_MSB 46 232 #define RX_ATTENTION_ORDER_MASK 0x0000400000000000 233 234 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 235 #define RX_ATTENTION_CCE_MATCH_LSB 47 236 #define RX_ATTENTION_CCE_MATCH_MSB 47 237 #define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 238 239 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 240 #define RX_ATTENTION_OVERFLOW_ERR_LSB 48 241 #define RX_ATTENTION_OVERFLOW_ERR_MSB 48 242 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 243 244 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 245 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 246 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 247 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 248 249 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 250 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 251 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 252 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 253 254 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 255 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 256 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 257 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 258 259 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 260 #define RX_ATTENTION_SA_IDX_INVALID_LSB 52 261 #define RX_ATTENTION_SA_IDX_INVALID_MSB 52 262 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 263 264 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 265 #define RX_ATTENTION_DA_IDX_INVALID_LSB 53 266 #define RX_ATTENTION_DA_IDX_INVALID_MSB 53 267 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 268 269 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 270 #define RX_ATTENTION_RESERVED_1B_LSB 54 271 #define RX_ATTENTION_RESERVED_1B_MSB 54 272 #define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 273 274 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 275 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 276 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 277 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 278 279 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 280 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 281 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 282 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 283 284 #define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 285 #define RX_ATTENTION_DIRECTED_LSB 57 286 #define RX_ATTENTION_DIRECTED_MSB 57 287 #define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 288 289 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 290 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 291 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 292 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 293 294 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 295 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 296 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 297 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 298 299 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 300 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 301 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 302 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 303 304 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 305 #define RX_ATTENTION_DECRYPT_ERR_LSB 61 306 #define RX_ATTENTION_DECRYPT_ERR_MSB 61 307 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 308 309 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 310 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 311 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 312 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 313 314 #define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 315 #define RX_ATTENTION_FCS_ERR_LSB 63 316 #define RX_ATTENTION_FCS_ERR_MSB 63 317 #define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 318 319 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 320 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 321 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 322 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 323 324 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 325 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 326 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 327 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 328 329 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 330 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 331 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 332 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 333 334 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 335 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 336 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 337 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 338 339 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 340 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 341 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 342 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 343 344 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 345 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 346 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 347 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 348 349 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 350 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 351 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 352 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 353 354 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 355 #define RX_ATTENTION_DA_IS_VALID_LSB 7 356 #define RX_ATTENTION_DA_IS_VALID_MSB 7 357 #define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 358 359 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 360 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 361 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 362 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 363 364 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 365 #define RX_ATTENTION_SA_IS_VALID_LSB 9 366 #define RX_ATTENTION_SA_IS_VALID_MSB 9 367 #define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 368 369 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 370 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 371 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 372 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 373 374 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 375 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 376 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 377 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 378 379 #define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 380 #define RX_ATTENTION_RESERVED_2_LSB 14 381 #define RX_ATTENTION_RESERVED_2_MSB 30 382 #define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 383 384 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 385 #define RX_ATTENTION_MSDU_DONE_LSB 31 386 #define RX_ATTENTION_MSDU_DONE_MSB 31 387 #define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 388 389 #define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 390 #define RX_ATTENTION_TLV64_PADDING_LSB 32 391 #define RX_ATTENTION_TLV64_PADDING_MSB 63 392 #define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 393 394 #endif 395