1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _RX_FRAME_1K_BITMAP_ACK_H_ 21 #define _RX_FRAME_1K_BITMAP_ACK_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 26 27 #define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 28 29 struct rx_frame_1k_bitmap_ack { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t reserved_0a : 5, 32 ba_bitmap_size : 2, 33 reserved_0b : 3, 34 ba_tid : 4, 35 sta_full_aid : 13, 36 reserved_0c : 5; 37 uint32_t addr1_31_0 : 32; 38 uint32_t addr1_47_32 : 16, 39 addr2_15_0 : 16; 40 uint32_t addr2_47_16 : 32; 41 uint32_t ba_ts_ctrl : 16, 42 ba_ts_seq : 16; 43 uint32_t ba_ts_bitmap_31_0 : 32; 44 uint32_t ba_ts_bitmap_63_32 : 32; 45 uint32_t ba_ts_bitmap_95_64 : 32; 46 uint32_t ba_ts_bitmap_127_96 : 32; 47 uint32_t ba_ts_bitmap_159_128 : 32; 48 uint32_t ba_ts_bitmap_191_160 : 32; 49 uint32_t ba_ts_bitmap_223_192 : 32; 50 uint32_t ba_ts_bitmap_255_224 : 32; 51 uint32_t ba_ts_bitmap_287_256 : 32; 52 uint32_t ba_ts_bitmap_319_288 : 32; 53 uint32_t ba_ts_bitmap_351_320 : 32; 54 uint32_t ba_ts_bitmap_383_352 : 32; 55 uint32_t ba_ts_bitmap_415_384 : 32; 56 uint32_t ba_ts_bitmap_447_416 : 32; 57 uint32_t ba_ts_bitmap_479_448 : 32; 58 uint32_t ba_ts_bitmap_511_480 : 32; 59 uint32_t ba_ts_bitmap_543_512 : 32; 60 uint32_t ba_ts_bitmap_575_544 : 32; 61 uint32_t ba_ts_bitmap_607_576 : 32; 62 uint32_t ba_ts_bitmap_639_608 : 32; 63 uint32_t ba_ts_bitmap_671_640 : 32; 64 uint32_t ba_ts_bitmap_703_672 : 32; 65 uint32_t ba_ts_bitmap_735_704 : 32; 66 uint32_t ba_ts_bitmap_767_736 : 32; 67 uint32_t ba_ts_bitmap_799_768 : 32; 68 uint32_t ba_ts_bitmap_831_800 : 32; 69 uint32_t ba_ts_bitmap_863_832 : 32; 70 uint32_t ba_ts_bitmap_895_864 : 32; 71 uint32_t ba_ts_bitmap_927_896 : 32; 72 uint32_t ba_ts_bitmap_959_928 : 32; 73 uint32_t ba_ts_bitmap_991_960 : 32; 74 uint32_t ba_ts_bitmap_1023_992 : 32; 75 uint32_t tlv64_padding : 32; 76 #else 77 uint32_t reserved_0c : 5, 78 sta_full_aid : 13, 79 ba_tid : 4, 80 reserved_0b : 3, 81 ba_bitmap_size : 2, 82 reserved_0a : 5; 83 uint32_t addr1_31_0 : 32; 84 uint32_t addr2_15_0 : 16, 85 addr1_47_32 : 16; 86 uint32_t addr2_47_16 : 32; 87 uint32_t ba_ts_seq : 16, 88 ba_ts_ctrl : 16; 89 uint32_t ba_ts_bitmap_31_0 : 32; 90 uint32_t ba_ts_bitmap_63_32 : 32; 91 uint32_t ba_ts_bitmap_95_64 : 32; 92 uint32_t ba_ts_bitmap_127_96 : 32; 93 uint32_t ba_ts_bitmap_159_128 : 32; 94 uint32_t ba_ts_bitmap_191_160 : 32; 95 uint32_t ba_ts_bitmap_223_192 : 32; 96 uint32_t ba_ts_bitmap_255_224 : 32; 97 uint32_t ba_ts_bitmap_287_256 : 32; 98 uint32_t ba_ts_bitmap_319_288 : 32; 99 uint32_t ba_ts_bitmap_351_320 : 32; 100 uint32_t ba_ts_bitmap_383_352 : 32; 101 uint32_t ba_ts_bitmap_415_384 : 32; 102 uint32_t ba_ts_bitmap_447_416 : 32; 103 uint32_t ba_ts_bitmap_479_448 : 32; 104 uint32_t ba_ts_bitmap_511_480 : 32; 105 uint32_t ba_ts_bitmap_543_512 : 32; 106 uint32_t ba_ts_bitmap_575_544 : 32; 107 uint32_t ba_ts_bitmap_607_576 : 32; 108 uint32_t ba_ts_bitmap_639_608 : 32; 109 uint32_t ba_ts_bitmap_671_640 : 32; 110 uint32_t ba_ts_bitmap_703_672 : 32; 111 uint32_t ba_ts_bitmap_735_704 : 32; 112 uint32_t ba_ts_bitmap_767_736 : 32; 113 uint32_t ba_ts_bitmap_799_768 : 32; 114 uint32_t ba_ts_bitmap_831_800 : 32; 115 uint32_t ba_ts_bitmap_863_832 : 32; 116 uint32_t ba_ts_bitmap_895_864 : 32; 117 uint32_t ba_ts_bitmap_927_896 : 32; 118 uint32_t ba_ts_bitmap_959_928 : 32; 119 uint32_t ba_ts_bitmap_991_960 : 32; 120 uint32_t ba_ts_bitmap_1023_992 : 32; 121 uint32_t tlv64_padding : 32; 122 #endif 123 }; 124 125 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 126 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 127 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 128 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f 129 130 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 131 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 132 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 133 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 134 135 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 136 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 137 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 138 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 139 140 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 141 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 142 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 143 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 144 145 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 146 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 147 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 148 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 149 150 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 151 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 152 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 153 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 154 155 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 156 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 157 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 158 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 159 160 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 161 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 162 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 163 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 164 165 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 166 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 167 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 168 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 169 170 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 171 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 172 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 173 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 174 175 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 176 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 177 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 178 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 179 180 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 181 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 182 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 183 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 184 185 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 186 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 187 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 188 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 189 190 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 191 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 192 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 193 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 194 195 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 196 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 197 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 198 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 199 200 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 201 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 202 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 203 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 204 205 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 206 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 207 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 208 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 209 210 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 211 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 212 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 213 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 214 215 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 216 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 217 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 218 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 219 220 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 221 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 222 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 223 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 224 225 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 226 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 227 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 228 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 229 230 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 231 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 232 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 233 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff 234 235 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 236 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 237 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 238 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 239 240 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 241 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 242 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 243 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff 244 245 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 246 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 247 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 248 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 249 250 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 251 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 252 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 253 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff 254 255 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 256 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 257 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 258 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 259 260 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 261 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 262 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 263 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff 264 265 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 266 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 267 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 268 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 269 270 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 271 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 272 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 273 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff 274 275 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 276 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 277 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 278 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 279 280 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 281 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 282 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 283 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff 284 285 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 286 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 287 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 288 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 289 290 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 291 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 292 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 293 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff 294 295 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 296 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 297 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 298 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 299 300 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 301 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 302 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 303 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff 304 305 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 306 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 307 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 308 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 309 310 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 311 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 312 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 313 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff 314 315 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 316 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 317 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 318 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 319 320 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 321 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 322 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 323 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff 324 325 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 326 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 327 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 328 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 329 330 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 331 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 332 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 333 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff 334 335 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 336 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 337 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 338 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 339 340 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 341 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 342 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 343 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff 344 345 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 346 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 347 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 348 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 349 350 #endif 351