1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MPDU_END_H_ 23 #define _RX_MPDU_END_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_MPDU_END 4 28 29 #define NUM_OF_QWORDS_RX_MPDU_END 2 30 31 struct rx_mpdu_end { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 uint32_t rxpcu_mpdu_filter_in_category : 2, 34 sw_frame_group_id : 7, 35 reserved_0 : 7, 36 phy_ppdu_id : 16; 37 uint32_t reserved_1a : 11, 38 unsup_ktype_short_frame : 1, 39 rx_in_tx_decrypt_byp : 1, 40 overflow_err : 1, 41 mpdu_length_err : 1, 42 tkip_mic_err : 1, 43 decrypt_err : 1, 44 unencrypted_frame_err : 1, 45 pn_fields_contain_valid_info : 1, 46 fcs_err : 1, 47 msdu_length_err : 1, 48 rxdma0_destination_ring : 3, 49 rxdma1_destination_ring : 3, 50 decrypt_status_code : 3, 51 rx_bitmap_not_updated : 1, 52 reserved_1b : 1; 53 uint32_t reserved_2a : 15, 54 rxpcu_mgmt_sequence_nr_valid : 1, 55 rxpcu_mgmt_sequence_nr : 16; 56 uint32_t __reserved_g_0002 : 32; 57 #else 58 uint32_t phy_ppdu_id : 16, 59 reserved_0 : 7, 60 sw_frame_group_id : 7, 61 rxpcu_mpdu_filter_in_category : 2; 62 uint32_t reserved_1b : 1, 63 rx_bitmap_not_updated : 1, 64 decrypt_status_code : 3, 65 rxdma1_destination_ring : 3, 66 rxdma0_destination_ring : 3, 67 msdu_length_err : 1, 68 fcs_err : 1, 69 pn_fields_contain_valid_info : 1, 70 unencrypted_frame_err : 1, 71 decrypt_err : 1, 72 tkip_mic_err : 1, 73 mpdu_length_err : 1, 74 overflow_err : 1, 75 rx_in_tx_decrypt_byp : 1, 76 unsup_ktype_short_frame : 1, 77 reserved_1a : 11; 78 uint32_t rxpcu_mgmt_sequence_nr : 16, 79 rxpcu_mgmt_sequence_nr_valid : 1, 80 reserved_2a : 15; 81 uint32_t __reserved_g_0002 : 32; 82 #endif 83 }; 84 85 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 86 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 87 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 88 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 89 90 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 91 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 92 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 93 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 94 95 #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 96 #define RX_MPDU_END_RESERVED_0_LSB 9 97 #define RX_MPDU_END_RESERVED_0_MSB 15 98 #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 99 100 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 101 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 102 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 103 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 104 105 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 106 #define RX_MPDU_END_RESERVED_1A_LSB 32 107 #define RX_MPDU_END_RESERVED_1A_MSB 42 108 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 109 110 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 111 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 112 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 113 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 114 115 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 116 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 117 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 118 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 119 120 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 121 #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 122 #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 123 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 124 125 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 126 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 127 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 128 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 129 130 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 131 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 132 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 133 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 134 135 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 136 #define RX_MPDU_END_DECRYPT_ERR_LSB 48 137 #define RX_MPDU_END_DECRYPT_ERR_MSB 48 138 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 139 140 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 141 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 142 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 143 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 144 145 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 146 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 147 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 148 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 149 150 #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 151 #define RX_MPDU_END_FCS_ERR_LSB 51 152 #define RX_MPDU_END_FCS_ERR_MSB 51 153 #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 154 155 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 156 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 157 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 158 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 159 160 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 161 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 162 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 163 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 164 165 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 166 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 167 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 168 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 169 170 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 171 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 172 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 173 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 174 175 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 176 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 177 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 178 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 179 180 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 181 #define RX_MPDU_END_RESERVED_1B_LSB 63 182 #define RX_MPDU_END_RESERVED_1B_MSB 63 183 #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 184 185 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 186 #define RX_MPDU_END_RESERVED_2A_LSB 0 187 #define RX_MPDU_END_RESERVED_2A_MSB 14 188 #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 189 190 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 191 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 192 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 193 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 194 195 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 196 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 197 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 198 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 199 200 #endif 201