1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MPDU_INFO_H_ 23 #define _RX_MPDU_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rxpt_classify_info.h" 28 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 29 30 struct rx_mpdu_info { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct rxpt_classify_info rxpt_classify_info_details; 33 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 34 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 35 receive_queue_number : 16, 36 pre_delim_err_warning : 1, 37 first_delim_err : 1, 38 reserved_2a : 6; 39 uint32_t pn_31_0 : 32; 40 uint32_t pn_63_32 : 32; 41 uint32_t pn_95_64 : 32; 42 uint32_t pn_127_96 : 32; 43 uint32_t epd_en : 1, 44 all_frames_shall_be_encrypted : 1, 45 encrypt_type : 4, 46 wep_key_width_for_variable_key : 2, 47 __reserved_g_0003 : 2, 48 bssid_hit : 1, 49 bssid_number : 4, 50 tid : 4, 51 reserved_7a : 13; 52 uint32_t peer_meta_data : 32; 53 uint32_t rxpcu_mpdu_filter_in_category : 2, 54 sw_frame_group_id : 7, 55 ndp_frame : 1, 56 phy_err : 1, 57 phy_err_during_mpdu_header : 1, 58 protocol_version_err : 1, 59 ast_based_lookup_valid : 1, 60 __reserved_g_0005 : 1, 61 reserved_9a : 1, 62 phy_ppdu_id : 16; 63 uint32_t ast_index : 16, 64 sw_peer_id : 16; 65 uint32_t mpdu_frame_control_valid : 1, 66 mpdu_duration_valid : 1, 67 mac_addr_ad1_valid : 1, 68 mac_addr_ad2_valid : 1, 69 mac_addr_ad3_valid : 1, 70 mac_addr_ad4_valid : 1, 71 mpdu_sequence_control_valid : 1, 72 mpdu_qos_control_valid : 1, 73 mpdu_ht_control_valid : 1, 74 frame_encryption_info_valid : 1, 75 mpdu_fragment_number : 4, 76 more_fragment_flag : 1, 77 reserved_11a : 1, 78 fr_ds : 1, 79 to_ds : 1, 80 encrypted : 1, 81 mpdu_retry : 1, 82 mpdu_sequence_number : 12; 83 uint32_t key_id_octet : 8, 84 new_peer_entry : 1, 85 decrypt_needed : 1, 86 decap_type : 2, 87 rx_insert_vlan_c_tag_padding : 1, 88 rx_insert_vlan_s_tag_padding : 1, 89 strip_vlan_c_tag_decap : 1, 90 strip_vlan_s_tag_decap : 1, 91 pre_delim_count : 12, 92 ampdu_flag : 1, 93 bar_frame : 1, 94 raw_mpdu : 1, 95 reserved_12 : 1; 96 uint32_t mpdu_length : 14, 97 first_mpdu : 1, 98 mcast_bcast : 1, 99 ast_index_not_found : 1, 100 ast_index_timeout : 1, 101 power_mgmt : 1, 102 non_qos : 1, 103 null_data : 1, 104 mgmt_type : 1, 105 ctrl_type : 1, 106 more_data : 1, 107 eosp : 1, 108 fragment_flag : 1, 109 order : 1, 110 u_apsd_trigger : 1, 111 encrypt_required : 1, 112 directed : 1, 113 amsdu_present : 1, 114 reserved_13 : 1; 115 uint32_t mpdu_frame_control_field : 16, 116 mpdu_duration_field : 16; 117 uint32_t mac_addr_ad1_31_0 : 32; 118 uint32_t mac_addr_ad1_47_32 : 16, 119 mac_addr_ad2_15_0 : 16; 120 uint32_t mac_addr_ad2_47_16 : 32; 121 uint32_t mac_addr_ad3_31_0 : 32; 122 uint32_t mac_addr_ad3_47_32 : 16, 123 mpdu_sequence_control_field : 16; 124 uint32_t mac_addr_ad4_31_0 : 32; 125 uint32_t mac_addr_ad4_47_32 : 16, 126 mpdu_qos_control_field : 16; 127 uint32_t mpdu_ht_control_field : 32; 128 uint32_t vdev_id : 8, 129 service_code : 9, 130 priority_valid : 1, 131 src_info : 12, 132 reserved_23a : 1, 133 __reserved_g_0006 : 1; 134 uint32_t __reserved_g_0007 : 32; 135 uint32_t __reserved_g_0008 : 16, 136 __reserved_g_0009 : 16; 137 uint32_t __reserved_g_0010 : 32; 138 uint32_t authorized_to_send_wds : 1, 139 reserved_27a : 31; 140 uint32_t reserved_28a : 32; 141 uint32_t reserved_29a : 32; 142 #else 143 struct rxpt_classify_info rxpt_classify_info_details; 144 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 145 uint32_t reserved_2a : 6, 146 first_delim_err : 1, 147 pre_delim_err_warning : 1, 148 receive_queue_number : 16, 149 rx_reo_queue_desc_addr_39_32 : 8; 150 uint32_t pn_31_0 : 32; 151 uint32_t pn_63_32 : 32; 152 uint32_t pn_95_64 : 32; 153 uint32_t pn_127_96 : 32; 154 uint32_t reserved_7a : 13, 155 tid : 4, 156 bssid_number : 4, 157 bssid_hit : 1, 158 __reserved_g_0003 : 2, 159 wep_key_width_for_variable_key : 2, 160 encrypt_type : 4, 161 all_frames_shall_be_encrypted : 1, 162 epd_en : 1; 163 uint32_t peer_meta_data : 32; 164 uint32_t phy_ppdu_id : 16, 165 reserved_9a : 1, 166 __reserved_g_0005 : 1, 167 ast_based_lookup_valid : 1, 168 protocol_version_err : 1, 169 phy_err_during_mpdu_header : 1, 170 phy_err : 1, 171 ndp_frame : 1, 172 sw_frame_group_id : 7, 173 rxpcu_mpdu_filter_in_category : 2; 174 uint32_t sw_peer_id : 16, 175 ast_index : 16; 176 uint32_t mpdu_sequence_number : 12, 177 mpdu_retry : 1, 178 encrypted : 1, 179 to_ds : 1, 180 fr_ds : 1, 181 reserved_11a : 1, 182 more_fragment_flag : 1, 183 mpdu_fragment_number : 4, 184 frame_encryption_info_valid : 1, 185 mpdu_ht_control_valid : 1, 186 mpdu_qos_control_valid : 1, 187 mpdu_sequence_control_valid : 1, 188 mac_addr_ad4_valid : 1, 189 mac_addr_ad3_valid : 1, 190 mac_addr_ad2_valid : 1, 191 mac_addr_ad1_valid : 1, 192 mpdu_duration_valid : 1, 193 mpdu_frame_control_valid : 1; 194 uint32_t reserved_12 : 1, 195 raw_mpdu : 1, 196 bar_frame : 1, 197 ampdu_flag : 1, 198 pre_delim_count : 12, 199 strip_vlan_s_tag_decap : 1, 200 strip_vlan_c_tag_decap : 1, 201 rx_insert_vlan_s_tag_padding : 1, 202 rx_insert_vlan_c_tag_padding : 1, 203 decap_type : 2, 204 decrypt_needed : 1, 205 new_peer_entry : 1, 206 key_id_octet : 8; 207 uint32_t reserved_13 : 1, 208 amsdu_present : 1, 209 directed : 1, 210 encrypt_required : 1, 211 u_apsd_trigger : 1, 212 order : 1, 213 fragment_flag : 1, 214 eosp : 1, 215 more_data : 1, 216 ctrl_type : 1, 217 mgmt_type : 1, 218 null_data : 1, 219 non_qos : 1, 220 power_mgmt : 1, 221 ast_index_timeout : 1, 222 ast_index_not_found : 1, 223 mcast_bcast : 1, 224 first_mpdu : 1, 225 mpdu_length : 14; 226 uint32_t mpdu_duration_field : 16, 227 mpdu_frame_control_field : 16; 228 uint32_t mac_addr_ad1_31_0 : 32; 229 uint32_t mac_addr_ad2_15_0 : 16, 230 mac_addr_ad1_47_32 : 16; 231 uint32_t mac_addr_ad2_47_16 : 32; 232 uint32_t mac_addr_ad3_31_0 : 32; 233 uint32_t mpdu_sequence_control_field : 16, 234 mac_addr_ad3_47_32 : 16; 235 uint32_t mac_addr_ad4_31_0 : 32; 236 uint32_t mpdu_qos_control_field : 16, 237 mac_addr_ad4_47_32 : 16; 238 uint32_t mpdu_ht_control_field : 32; 239 uint32_t __reserved_g_0006 : 1, 240 reserved_23a : 1, 241 src_info : 12, 242 priority_valid : 1, 243 service_code : 9, 244 vdev_id : 8; 245 uint32_t __reserved_g_0007 : 32; 246 uint32_t __reserved_g_0009 : 16, 247 __reserved_g_0008 : 16; 248 uint32_t __reserved_g_0010 : 32; 249 uint32_t reserved_27a : 31, 250 authorized_to_send_wds : 1; 251 uint32_t reserved_28a : 32; 252 uint32_t reserved_29a : 32; 253 #endif 254 }; 255 256 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 257 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 258 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 259 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 260 261 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 262 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 263 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 264 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 265 266 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 267 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 268 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 269 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 270 271 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 272 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 273 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 274 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 275 276 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 277 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 278 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 279 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 280 281 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 282 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 283 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 284 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 285 286 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 287 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 288 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 289 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 290 291 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 292 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 293 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 294 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 295 296 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 297 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 298 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 299 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 300 301 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 302 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 303 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 304 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 305 306 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 307 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 308 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 309 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 310 311 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 312 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 313 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 314 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 315 316 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 317 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 318 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 319 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 320 321 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 322 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 323 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 324 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 325 326 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 327 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 328 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 329 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 330 331 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 332 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 333 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 334 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 335 336 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 337 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 338 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 339 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 340 341 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 342 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 343 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 344 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 345 346 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 347 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 348 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 349 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 350 351 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 352 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 353 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 354 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 355 356 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c 357 #define RX_MPDU_INFO_PN_31_0_LSB 0 358 #define RX_MPDU_INFO_PN_31_0_MSB 31 359 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 360 361 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 362 #define RX_MPDU_INFO_PN_63_32_LSB 0 363 #define RX_MPDU_INFO_PN_63_32_MSB 31 364 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 365 366 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 367 #define RX_MPDU_INFO_PN_95_64_LSB 0 368 #define RX_MPDU_INFO_PN_95_64_MSB 31 369 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 370 371 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 372 #define RX_MPDU_INFO_PN_127_96_LSB 0 373 #define RX_MPDU_INFO_PN_127_96_MSB 31 374 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 375 376 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c 377 #define RX_MPDU_INFO_EPD_EN_LSB 0 378 #define RX_MPDU_INFO_EPD_EN_MSB 0 379 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 380 381 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 382 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 383 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 384 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 385 386 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c 387 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 388 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 389 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 390 391 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 392 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 393 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 394 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 395 396 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c 397 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 398 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 399 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 400 401 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c 402 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 403 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 404 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 405 406 #define RX_MPDU_INFO_TID_OFFSET 0x0000001c 407 #define RX_MPDU_INFO_TID_LSB 15 408 #define RX_MPDU_INFO_TID_MSB 18 409 #define RX_MPDU_INFO_TID_MASK 0x00078000 410 411 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c 412 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 413 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 414 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 415 416 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 417 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 418 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 419 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 420 421 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 422 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 423 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 424 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 425 426 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 427 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 428 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 429 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 430 431 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 432 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 433 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 434 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 435 436 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 437 #define RX_MPDU_INFO_PHY_ERR_LSB 10 438 #define RX_MPDU_INFO_PHY_ERR_MSB 10 439 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 440 441 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 442 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 443 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 444 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 445 446 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 447 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 448 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 449 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 450 451 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 452 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 453 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 454 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 455 456 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 457 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 458 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 459 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 460 461 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 462 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 463 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 464 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 465 466 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 467 #define RX_MPDU_INFO_AST_INDEX_LSB 0 468 #define RX_MPDU_INFO_AST_INDEX_MSB 15 469 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 470 471 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 472 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 473 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 474 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 475 476 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 477 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 478 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 479 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 480 481 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c 482 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 483 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 484 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 485 486 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 487 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 488 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 489 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 490 491 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 492 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 493 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 494 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 495 496 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 497 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 498 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 499 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 500 501 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 502 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 503 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 504 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 505 506 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 507 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 508 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 509 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 510 511 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 512 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 513 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 514 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 515 516 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 517 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 518 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 519 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 520 521 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 522 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 523 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 524 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 525 526 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 527 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 528 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 529 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 530 531 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 532 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 533 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 534 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 535 536 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c 537 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 538 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 539 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 540 541 #define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c 542 #define RX_MPDU_INFO_FR_DS_LSB 16 543 #define RX_MPDU_INFO_FR_DS_MSB 16 544 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 545 546 #define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c 547 #define RX_MPDU_INFO_TO_DS_LSB 17 548 #define RX_MPDU_INFO_TO_DS_MSB 17 549 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 550 551 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c 552 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 553 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 554 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 555 556 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c 557 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 558 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 559 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 560 561 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 562 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 563 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 564 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 565 566 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 567 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 568 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 569 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 570 571 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 572 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 573 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 574 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 575 576 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 577 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 578 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 579 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 580 581 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 582 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 583 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 584 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 585 586 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 587 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 588 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 589 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 590 591 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 592 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 593 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 594 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 595 596 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 597 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 598 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 599 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 600 601 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 602 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 603 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 604 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 605 606 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 607 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 608 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 609 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 610 611 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 612 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 613 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 614 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 615 616 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 617 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 618 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 619 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 620 621 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 622 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 623 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 624 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 625 626 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 627 #define RX_MPDU_INFO_RESERVED_12_LSB 31 628 #define RX_MPDU_INFO_RESERVED_12_MSB 31 629 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 630 631 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 632 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 633 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 634 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 635 636 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 637 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 638 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 639 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 640 641 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 642 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 643 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 644 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 645 646 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 647 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 648 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 649 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 650 651 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 652 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 653 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 654 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 655 656 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 657 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 658 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 659 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 660 661 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 662 #define RX_MPDU_INFO_NON_QOS_LSB 19 663 #define RX_MPDU_INFO_NON_QOS_MSB 19 664 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 665 666 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 667 #define RX_MPDU_INFO_NULL_DATA_LSB 20 668 #define RX_MPDU_INFO_NULL_DATA_MSB 20 669 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 670 671 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 672 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 673 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 674 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 675 676 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 677 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 678 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 679 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 680 681 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 682 #define RX_MPDU_INFO_MORE_DATA_LSB 23 683 #define RX_MPDU_INFO_MORE_DATA_MSB 23 684 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 685 686 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 687 #define RX_MPDU_INFO_EOSP_LSB 24 688 #define RX_MPDU_INFO_EOSP_MSB 24 689 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 690 691 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 692 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 693 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 694 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 695 696 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 697 #define RX_MPDU_INFO_ORDER_LSB 26 698 #define RX_MPDU_INFO_ORDER_MSB 26 699 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 700 701 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 702 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 703 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 704 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 705 706 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 707 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 708 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 709 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 710 711 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 712 #define RX_MPDU_INFO_DIRECTED_LSB 29 713 #define RX_MPDU_INFO_DIRECTED_MSB 29 714 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 715 716 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 717 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 718 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 719 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 720 721 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 722 #define RX_MPDU_INFO_RESERVED_13_LSB 31 723 #define RX_MPDU_INFO_RESERVED_13_MSB 31 724 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 725 726 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 727 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 728 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 729 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 730 731 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 732 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 733 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 734 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 735 736 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 737 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 738 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 739 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 740 741 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 742 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 743 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 744 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 745 746 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 747 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 748 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 749 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 750 751 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 752 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 753 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 754 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 755 756 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 757 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 758 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 759 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 760 761 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 762 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 763 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 764 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 765 766 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 767 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 768 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 769 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 770 771 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 772 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 773 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 774 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 775 776 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 777 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 778 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 779 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 780 781 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 782 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 783 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 784 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 785 786 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 787 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 788 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 789 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 790 791 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 792 #define RX_MPDU_INFO_VDEV_ID_LSB 0 793 #define RX_MPDU_INFO_VDEV_ID_MSB 7 794 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 795 796 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 797 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 798 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 799 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 800 801 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 802 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 803 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 804 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 805 806 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 807 #define RX_MPDU_INFO_SRC_INFO_LSB 18 808 #define RX_MPDU_INFO_SRC_INFO_MSB 29 809 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 810 811 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 812 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 813 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 814 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 815 816 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c 817 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 818 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 819 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 820 821 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 822 #define RX_MPDU_INFO_RESERVED_27A_LSB 1 823 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 824 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe 825 826 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 827 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 828 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 829 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 830 831 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 832 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 833 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 834 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 835 836 #endif 837