1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MSDU_DESC_INFO_H_ 23 #define _RX_MSDU_DESC_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 28 29 struct rx_msdu_desc_info { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t first_msdu_in_mpdu_flag : 1, 32 last_msdu_in_mpdu_flag : 1, 33 msdu_continuation : 1, 34 msdu_length : 14, 35 msdu_drop : 1, 36 sa_is_valid : 1, 37 da_is_valid : 1, 38 da_is_mcbc : 1, 39 l3_header_padding_msb : 1, 40 tcp_udp_chksum_fail : 1, 41 ip_chksum_fail : 1, 42 fr_ds : 1, 43 to_ds : 1, 44 intra_bss : 1, 45 dest_chip_id : 2, 46 decap_format : 2, 47 reserved_0a : 1; 48 #else 49 uint32_t reserved_0a : 1, 50 decap_format : 2, 51 dest_chip_id : 2, 52 intra_bss : 1, 53 to_ds : 1, 54 fr_ds : 1, 55 ip_chksum_fail : 1, 56 tcp_udp_chksum_fail : 1, 57 l3_header_padding_msb : 1, 58 da_is_mcbc : 1, 59 da_is_valid : 1, 60 sa_is_valid : 1, 61 msdu_drop : 1, 62 msdu_length : 14, 63 msdu_continuation : 1, 64 last_msdu_in_mpdu_flag : 1, 65 first_msdu_in_mpdu_flag : 1; 66 #endif 67 }; 68 69 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 70 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 71 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 72 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 73 74 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 75 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 76 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 77 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 78 79 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 80 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 81 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 82 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 83 84 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 85 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 86 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 87 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 88 89 #define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 90 #define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 91 #define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 92 #define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 93 94 #define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 95 #define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 96 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 97 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 98 99 #define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 100 #define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 101 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 102 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 103 104 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 105 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 106 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 107 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 108 109 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 110 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 111 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 112 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 113 114 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 115 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 116 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 117 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 118 119 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 120 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 121 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 122 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 123 124 #define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 125 #define RX_MSDU_DESC_INFO_FR_DS_LSB 24 126 #define RX_MSDU_DESC_INFO_FR_DS_MSB 24 127 #define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 128 129 #define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 130 #define RX_MSDU_DESC_INFO_TO_DS_LSB 25 131 #define RX_MSDU_DESC_INFO_TO_DS_MSB 25 132 #define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 133 134 #define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 135 #define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 136 #define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 137 #define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 138 139 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 140 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 141 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 142 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 143 144 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 145 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 146 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 147 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 148 149 #define RX_MSDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 150 #define RX_MSDU_DESC_INFO_RESERVED_0A_LSB 31 151 #define RX_MSDU_DESC_INFO_RESERVED_0A_MSB 31 152 #define RX_MSDU_DESC_INFO_RESERVED_0A_MASK 0x80000000 153 154 #endif 155