1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MSDU_END_H_ 23 #define _RX_MSDU_END_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_MSDU_END 32 28 29 #define NUM_OF_QWORDS_RX_MSDU_END 16 30 31 struct rx_msdu_end { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 uint32_t rxpcu_mpdu_filter_in_category : 2, 34 sw_frame_group_id : 7, 35 reserved_0 : 7, 36 phy_ppdu_id : 16; 37 uint32_t ip_hdr_chksum : 16, 38 reported_mpdu_length : 14, 39 reserved_1a : 2; 40 uint32_t reserved_2a : 8, 41 cce_super_rule : 6, 42 cce_classify_not_done_truncate : 1, 43 cce_classify_not_done_cce_dis : 1, 44 cumulative_l3_checksum : 16; 45 uint32_t rule_indication_31_0 : 32; 46 uint32_t ipv6_options_crc : 32; 47 uint32_t da_offset : 6, 48 sa_offset : 6, 49 da_offset_valid : 1, 50 sa_offset_valid : 1, 51 reserved_5a : 2, 52 l3_type : 16; 53 uint32_t rule_indication_63_32 : 32; 54 uint32_t tcp_seq_number : 32; 55 uint32_t tcp_ack_number : 32; 56 uint32_t tcp_flag : 9, 57 lro_eligible : 1, 58 reserved_9a : 6, 59 window_size : 16; 60 uint32_t sa_sw_peer_id : 16, 61 sa_idx_timeout : 1, 62 da_idx_timeout : 1, 63 to_ds : 1, 64 tid : 4, 65 sa_is_valid : 1, 66 da_is_valid : 1, 67 da_is_mcbc : 1, 68 l3_header_padding : 2, 69 first_msdu : 1, 70 last_msdu : 1, 71 fr_ds : 1, 72 ip_chksum_fail_copy : 1; 73 uint32_t sa_idx : 16, 74 da_idx_or_sw_peer_id : 16; 75 uint32_t msdu_drop : 1, 76 reo_destination_indication : 5, 77 flow_idx : 20, 78 use_ppe : 1, 79 __reserved_g_0003 : 2, 80 vlan_ctag_stripped : 1, 81 vlan_stag_stripped : 1, 82 fragment_flag : 1; 83 uint32_t fse_metadata : 32; 84 uint32_t cce_metadata : 16, 85 tcp_udp_chksum : 16; 86 uint32_t aggregation_count : 8, 87 flow_aggregation_continuation : 1, 88 fisa_timeout : 1, 89 tcp_udp_chksum_fail_copy : 1, 90 msdu_limit_error : 1, 91 flow_idx_timeout : 1, 92 flow_idx_invalid : 1, 93 cce_match : 1, 94 amsdu_parser_error : 1, 95 cumulative_ip_length : 16; 96 uint32_t key_id_octet : 8, 97 reserved_16a : 24; 98 uint32_t reserved_17a : 6, 99 service_code : 9, 100 priority_valid : 1, 101 intra_bss : 1, 102 dest_chip_id : 2, 103 multicast_echo : 1, 104 wds_learning_event : 1, 105 wds_roaming_event : 1, 106 wds_keep_alive_event : 1, 107 reserved_17b : 9; 108 uint32_t msdu_length : 14, 109 stbc : 1, 110 ipsec_esp : 1, 111 l3_offset : 7, 112 ipsec_ah : 1, 113 l4_offset : 8; 114 uint32_t msdu_number : 8, 115 decap_format : 2, 116 ipv4_proto : 1, 117 ipv6_proto : 1, 118 tcp_proto : 1, 119 udp_proto : 1, 120 ip_frag : 1, 121 tcp_only_ack : 1, 122 da_is_bcast_mcast : 1, 123 toeplitz_hash_sel : 2, 124 ip_fixed_header_valid : 1, 125 ip_extn_header_valid : 1, 126 tcp_udp_header_valid : 1, 127 mesh_control_present : 1, 128 ldpc : 1, 129 ip4_protocol_ip6_next_header : 8; 130 uint32_t vlan_ctag_ci : 16, 131 vlan_stag_ci : 16; 132 uint32_t peer_meta_data : 32; 133 uint32_t user_rssi : 8, 134 pkt_type : 4, 135 sgi : 2, 136 rate_mcs : 4, 137 receive_bandwidth : 3, 138 reception_type : 3, 139 mimo_ss_bitmap : 7, 140 msdu_done_copy : 1; 141 uint32_t flow_id_toeplitz : 32; 142 uint32_t ppdu_start_timestamp_63_32 : 32; 143 uint32_t sw_phy_meta_data : 32; 144 uint32_t ppdu_start_timestamp_31_0 : 32; 145 uint32_t toeplitz_hash_2_or_4 : 32; 146 uint32_t reserved_28a : 16, 147 sa_15_0 : 16; 148 uint32_t sa_47_16 : 32; 149 uint32_t first_mpdu : 1, 150 reserved_30a : 1, 151 mcast_bcast : 1, 152 ast_index_not_found : 1, 153 ast_index_timeout : 1, 154 power_mgmt : 1, 155 non_qos : 1, 156 null_data : 1, 157 mgmt_type : 1, 158 ctrl_type : 1, 159 more_data : 1, 160 eosp : 1, 161 a_msdu_error : 1, 162 reserved_30b : 1, 163 order : 1, 164 wifi_parser_error : 1, 165 overflow_err : 1, 166 msdu_length_err : 1, 167 tcp_udp_chksum_fail : 1, 168 ip_chksum_fail : 1, 169 sa_idx_invalid : 1, 170 da_idx_invalid : 1, 171 amsdu_addr_mismatch : 1, 172 rx_in_tx_decrypt_byp : 1, 173 encrypt_required : 1, 174 directed : 1, 175 buffer_fragment : 1, 176 mpdu_length_err : 1, 177 tkip_mic_err : 1, 178 decrypt_err : 1, 179 unencrypted_frame_err : 1, 180 fcs_err : 1; 181 uint32_t reserved_31a : 10, 182 decrypt_status_code : 3, 183 rx_bitmap_not_updated : 1, 184 reserved_31b : 17, 185 msdu_done : 1; 186 #else 187 uint32_t phy_ppdu_id : 16, 188 reserved_0 : 7, 189 sw_frame_group_id : 7, 190 rxpcu_mpdu_filter_in_category : 2; 191 uint32_t reserved_1a : 2, 192 reported_mpdu_length : 14, 193 ip_hdr_chksum : 16; 194 uint32_t cumulative_l3_checksum : 16, 195 cce_classify_not_done_cce_dis : 1, 196 cce_classify_not_done_truncate : 1, 197 cce_super_rule : 6, 198 reserved_2a : 8; 199 uint32_t rule_indication_31_0 : 32; 200 uint32_t ipv6_options_crc : 32; 201 uint32_t l3_type : 16, 202 reserved_5a : 2, 203 sa_offset_valid : 1, 204 da_offset_valid : 1, 205 sa_offset : 6, 206 da_offset : 6; 207 uint32_t rule_indication_63_32 : 32; 208 uint32_t tcp_seq_number : 32; 209 uint32_t tcp_ack_number : 32; 210 uint32_t window_size : 16, 211 reserved_9a : 6, 212 lro_eligible : 1, 213 tcp_flag : 9; 214 uint32_t ip_chksum_fail_copy : 1, 215 fr_ds : 1, 216 last_msdu : 1, 217 first_msdu : 1, 218 l3_header_padding : 2, 219 da_is_mcbc : 1, 220 da_is_valid : 1, 221 sa_is_valid : 1, 222 tid : 4, 223 to_ds : 1, 224 da_idx_timeout : 1, 225 sa_idx_timeout : 1, 226 sa_sw_peer_id : 16; 227 uint32_t da_idx_or_sw_peer_id : 16, 228 sa_idx : 16; 229 uint32_t fragment_flag : 1, 230 vlan_stag_stripped : 1, 231 vlan_ctag_stripped : 1, 232 __reserved_g_0003 : 2, 233 use_ppe : 1, 234 flow_idx : 20, 235 reo_destination_indication : 5, 236 msdu_drop : 1; 237 uint32_t fse_metadata : 32; 238 uint32_t tcp_udp_chksum : 16, 239 cce_metadata : 16; 240 uint32_t cumulative_ip_length : 16, 241 amsdu_parser_error : 1, 242 cce_match : 1, 243 flow_idx_invalid : 1, 244 flow_idx_timeout : 1, 245 msdu_limit_error : 1, 246 tcp_udp_chksum_fail_copy : 1, 247 fisa_timeout : 1, 248 flow_aggregation_continuation : 1, 249 aggregation_count : 8; 250 uint32_t reserved_16a : 24, 251 key_id_octet : 8; 252 uint32_t reserved_17b : 9, 253 wds_keep_alive_event : 1, 254 wds_roaming_event : 1, 255 wds_learning_event : 1, 256 multicast_echo : 1, 257 dest_chip_id : 2, 258 intra_bss : 1, 259 priority_valid : 1, 260 service_code : 9, 261 reserved_17a : 6; 262 uint32_t l4_offset : 8, 263 ipsec_ah : 1, 264 l3_offset : 7, 265 ipsec_esp : 1, 266 stbc : 1, 267 msdu_length : 14; 268 uint32_t ip4_protocol_ip6_next_header : 8, 269 ldpc : 1, 270 mesh_control_present : 1, 271 tcp_udp_header_valid : 1, 272 ip_extn_header_valid : 1, 273 ip_fixed_header_valid : 1, 274 toeplitz_hash_sel : 2, 275 da_is_bcast_mcast : 1, 276 tcp_only_ack : 1, 277 ip_frag : 1, 278 udp_proto : 1, 279 tcp_proto : 1, 280 ipv6_proto : 1, 281 ipv4_proto : 1, 282 decap_format : 2, 283 msdu_number : 8; 284 uint32_t vlan_stag_ci : 16, 285 vlan_ctag_ci : 16; 286 uint32_t peer_meta_data : 32; 287 uint32_t msdu_done_copy : 1, 288 mimo_ss_bitmap : 7, 289 reception_type : 3, 290 receive_bandwidth : 3, 291 rate_mcs : 4, 292 sgi : 2, 293 pkt_type : 4, 294 user_rssi : 8; 295 uint32_t flow_id_toeplitz : 32; 296 uint32_t ppdu_start_timestamp_63_32 : 32; 297 uint32_t sw_phy_meta_data : 32; 298 uint32_t ppdu_start_timestamp_31_0 : 32; 299 uint32_t toeplitz_hash_2_or_4 : 32; 300 uint32_t sa_15_0 : 16, 301 reserved_28a : 16; 302 uint32_t sa_47_16 : 32; 303 uint32_t fcs_err : 1, 304 unencrypted_frame_err : 1, 305 decrypt_err : 1, 306 tkip_mic_err : 1, 307 mpdu_length_err : 1, 308 buffer_fragment : 1, 309 directed : 1, 310 encrypt_required : 1, 311 rx_in_tx_decrypt_byp : 1, 312 amsdu_addr_mismatch : 1, 313 da_idx_invalid : 1, 314 sa_idx_invalid : 1, 315 ip_chksum_fail : 1, 316 tcp_udp_chksum_fail : 1, 317 msdu_length_err : 1, 318 overflow_err : 1, 319 wifi_parser_error : 1, 320 order : 1, 321 reserved_30b : 1, 322 a_msdu_error : 1, 323 eosp : 1, 324 more_data : 1, 325 ctrl_type : 1, 326 mgmt_type : 1, 327 null_data : 1, 328 non_qos : 1, 329 power_mgmt : 1, 330 ast_index_timeout : 1, 331 ast_index_not_found : 1, 332 mcast_bcast : 1, 333 reserved_30a : 1, 334 first_mpdu : 1; 335 uint32_t msdu_done : 1, 336 reserved_31b : 17, 337 rx_bitmap_not_updated : 1, 338 decrypt_status_code : 3, 339 reserved_31a : 10; 340 #endif 341 }; 342 343 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 344 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 345 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 346 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 347 348 #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 349 #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 350 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 351 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 352 353 #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 354 #define RX_MSDU_END_RESERVED_0_LSB 9 355 #define RX_MSDU_END_RESERVED_0_MSB 15 356 #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 357 358 #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 359 #define RX_MSDU_END_PHY_PPDU_ID_LSB 16 360 #define RX_MSDU_END_PHY_PPDU_ID_MSB 31 361 #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 362 363 #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 364 #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 365 #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 366 #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 367 368 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 369 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 370 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 371 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 372 373 #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 374 #define RX_MSDU_END_RESERVED_1A_LSB 62 375 #define RX_MSDU_END_RESERVED_1A_MSB 63 376 #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 377 378 #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 379 #define RX_MSDU_END_RESERVED_2A_LSB 0 380 #define RX_MSDU_END_RESERVED_2A_MSB 7 381 #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff 382 383 #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 384 #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 385 #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 386 #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 387 388 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 389 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 390 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 391 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 392 393 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 394 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 395 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 396 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 397 398 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 399 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 400 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 401 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 402 403 #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 404 #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 405 #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 406 #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 407 408 #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 409 #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 410 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 411 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff 412 413 #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 414 #define RX_MSDU_END_DA_OFFSET_LSB 32 415 #define RX_MSDU_END_DA_OFFSET_MSB 37 416 #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 417 418 #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 419 #define RX_MSDU_END_SA_OFFSET_LSB 38 420 #define RX_MSDU_END_SA_OFFSET_MSB 43 421 #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 422 423 #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 424 #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 425 #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 426 #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 427 428 #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 429 #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 430 #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 431 #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 432 433 #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 434 #define RX_MSDU_END_RESERVED_5A_LSB 46 435 #define RX_MSDU_END_RESERVED_5A_MSB 47 436 #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 437 438 #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 439 #define RX_MSDU_END_L3_TYPE_LSB 48 440 #define RX_MSDU_END_L3_TYPE_MSB 63 441 #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 442 443 #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 444 #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 445 #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 446 #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff 447 448 #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 449 #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 450 #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 451 #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 452 453 #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 454 #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 455 #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 456 #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff 457 458 #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 459 #define RX_MSDU_END_TCP_FLAG_LSB 32 460 #define RX_MSDU_END_TCP_FLAG_MSB 40 461 #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 462 463 #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 464 #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 465 #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 466 #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 467 468 #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 469 #define RX_MSDU_END_RESERVED_9A_LSB 42 470 #define RX_MSDU_END_RESERVED_9A_MSB 47 471 #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 472 473 #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 474 #define RX_MSDU_END_WINDOW_SIZE_LSB 48 475 #define RX_MSDU_END_WINDOW_SIZE_MSB 63 476 #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 477 478 #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 479 #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 480 #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 481 #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff 482 483 #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 484 #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 485 #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 486 #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 487 488 #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 489 #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 490 #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 491 #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 492 493 #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 494 #define RX_MSDU_END_TO_DS_LSB 18 495 #define RX_MSDU_END_TO_DS_MSB 18 496 #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 497 498 #define RX_MSDU_END_TID_OFFSET 0x0000000000000028 499 #define RX_MSDU_END_TID_LSB 19 500 #define RX_MSDU_END_TID_MSB 22 501 #define RX_MSDU_END_TID_MASK 0x0000000000780000 502 503 #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 504 #define RX_MSDU_END_SA_IS_VALID_LSB 23 505 #define RX_MSDU_END_SA_IS_VALID_MSB 23 506 #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 507 508 #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 509 #define RX_MSDU_END_DA_IS_VALID_LSB 24 510 #define RX_MSDU_END_DA_IS_VALID_MSB 24 511 #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 512 513 #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 514 #define RX_MSDU_END_DA_IS_MCBC_LSB 25 515 #define RX_MSDU_END_DA_IS_MCBC_MSB 25 516 #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 517 518 #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 519 #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 520 #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 521 #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 522 523 #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 524 #define RX_MSDU_END_FIRST_MSDU_LSB 28 525 #define RX_MSDU_END_FIRST_MSDU_MSB 28 526 #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 527 528 #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 529 #define RX_MSDU_END_LAST_MSDU_LSB 29 530 #define RX_MSDU_END_LAST_MSDU_MSB 29 531 #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 532 533 #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 534 #define RX_MSDU_END_FR_DS_LSB 30 535 #define RX_MSDU_END_FR_DS_MSB 30 536 #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 537 538 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 539 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 540 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 541 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 542 543 #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 544 #define RX_MSDU_END_SA_IDX_LSB 32 545 #define RX_MSDU_END_SA_IDX_MSB 47 546 #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 547 548 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 549 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 550 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 551 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 552 553 #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 554 #define RX_MSDU_END_MSDU_DROP_LSB 0 555 #define RX_MSDU_END_MSDU_DROP_MSB 0 556 #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 557 558 #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 559 #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 560 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 561 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e 562 563 #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 564 #define RX_MSDU_END_FLOW_IDX_LSB 6 565 #define RX_MSDU_END_FLOW_IDX_MSB 25 566 #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 567 568 #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 569 #define RX_MSDU_END_USE_PPE_LSB 26 570 #define RX_MSDU_END_USE_PPE_MSB 26 571 #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 572 573 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 574 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 575 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 576 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 577 578 #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 579 #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 580 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 581 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 582 583 #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 584 #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 585 #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 586 #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 587 588 #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 589 #define RX_MSDU_END_FSE_METADATA_LSB 32 590 #define RX_MSDU_END_FSE_METADATA_MSB 63 591 #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 592 593 #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 594 #define RX_MSDU_END_CCE_METADATA_LSB 0 595 #define RX_MSDU_END_CCE_METADATA_MSB 15 596 #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff 597 598 #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 599 #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 600 #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 601 #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 602 603 #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 604 #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 605 #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 606 #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 607 608 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 609 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 610 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 611 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 612 613 #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 614 #define RX_MSDU_END_FISA_TIMEOUT_LSB 41 615 #define RX_MSDU_END_FISA_TIMEOUT_MSB 41 616 #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 617 618 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 619 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 620 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 621 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 622 623 #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 624 #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 625 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 626 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 627 628 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 629 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 630 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 631 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 632 633 #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 634 #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 635 #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 636 #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 637 638 #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 639 #define RX_MSDU_END_CCE_MATCH_LSB 46 640 #define RX_MSDU_END_CCE_MATCH_MSB 46 641 #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 642 643 #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 644 #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 645 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 646 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 647 648 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 649 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 650 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 651 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 652 653 #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 654 #define RX_MSDU_END_KEY_ID_OCTET_LSB 0 655 #define RX_MSDU_END_KEY_ID_OCTET_MSB 7 656 #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff 657 658 #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 659 #define RX_MSDU_END_RESERVED_16A_LSB 8 660 #define RX_MSDU_END_RESERVED_16A_MSB 31 661 #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 662 663 #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 664 #define RX_MSDU_END_RESERVED_17A_LSB 32 665 #define RX_MSDU_END_RESERVED_17A_MSB 37 666 #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 667 668 #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 669 #define RX_MSDU_END_SERVICE_CODE_LSB 38 670 #define RX_MSDU_END_SERVICE_CODE_MSB 46 671 #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 672 673 #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 674 #define RX_MSDU_END_PRIORITY_VALID_LSB 47 675 #define RX_MSDU_END_PRIORITY_VALID_MSB 47 676 #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 677 678 #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 679 #define RX_MSDU_END_INTRA_BSS_LSB 48 680 #define RX_MSDU_END_INTRA_BSS_MSB 48 681 #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 682 683 #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 684 #define RX_MSDU_END_DEST_CHIP_ID_LSB 49 685 #define RX_MSDU_END_DEST_CHIP_ID_MSB 50 686 #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 687 688 #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 689 #define RX_MSDU_END_MULTICAST_ECHO_LSB 51 690 #define RX_MSDU_END_MULTICAST_ECHO_MSB 51 691 #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 692 693 #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 694 #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 695 #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 696 #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 697 698 #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 699 #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 700 #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 701 #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 702 703 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 704 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 705 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 706 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 707 708 #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 709 #define RX_MSDU_END_RESERVED_17B_LSB 55 710 #define RX_MSDU_END_RESERVED_17B_MSB 63 711 #define RX_MSDU_END_RESERVED_17B_MASK 0xff80000000000000 712 713 #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 714 #define RX_MSDU_END_MSDU_LENGTH_LSB 0 715 #define RX_MSDU_END_MSDU_LENGTH_MSB 13 716 #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff 717 718 #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 719 #define RX_MSDU_END_STBC_LSB 14 720 #define RX_MSDU_END_STBC_MSB 14 721 #define RX_MSDU_END_STBC_MASK 0x0000000000004000 722 723 #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 724 #define RX_MSDU_END_IPSEC_ESP_LSB 15 725 #define RX_MSDU_END_IPSEC_ESP_MSB 15 726 #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 727 728 #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 729 #define RX_MSDU_END_L3_OFFSET_LSB 16 730 #define RX_MSDU_END_L3_OFFSET_MSB 22 731 #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 732 733 #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 734 #define RX_MSDU_END_IPSEC_AH_LSB 23 735 #define RX_MSDU_END_IPSEC_AH_MSB 23 736 #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 737 738 #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 739 #define RX_MSDU_END_L4_OFFSET_LSB 24 740 #define RX_MSDU_END_L4_OFFSET_MSB 31 741 #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 742 743 #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 744 #define RX_MSDU_END_MSDU_NUMBER_LSB 32 745 #define RX_MSDU_END_MSDU_NUMBER_MSB 39 746 #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 747 748 #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 749 #define RX_MSDU_END_DECAP_FORMAT_LSB 40 750 #define RX_MSDU_END_DECAP_FORMAT_MSB 41 751 #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 752 753 #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 754 #define RX_MSDU_END_IPV4_PROTO_LSB 42 755 #define RX_MSDU_END_IPV4_PROTO_MSB 42 756 #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 757 758 #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 759 #define RX_MSDU_END_IPV6_PROTO_LSB 43 760 #define RX_MSDU_END_IPV6_PROTO_MSB 43 761 #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 762 763 #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 764 #define RX_MSDU_END_TCP_PROTO_LSB 44 765 #define RX_MSDU_END_TCP_PROTO_MSB 44 766 #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 767 768 #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 769 #define RX_MSDU_END_UDP_PROTO_LSB 45 770 #define RX_MSDU_END_UDP_PROTO_MSB 45 771 #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 772 773 #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 774 #define RX_MSDU_END_IP_FRAG_LSB 46 775 #define RX_MSDU_END_IP_FRAG_MSB 46 776 #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 777 778 #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 779 #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 780 #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 781 #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 782 783 #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 784 #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 785 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 786 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 787 788 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 789 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 790 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 791 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 792 793 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 794 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 795 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 796 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 797 798 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 799 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 800 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 801 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 802 803 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 804 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 805 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 806 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 807 808 #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 809 #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 810 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 811 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 812 813 #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 814 #define RX_MSDU_END_LDPC_LSB 55 815 #define RX_MSDU_END_LDPC_MSB 55 816 #define RX_MSDU_END_LDPC_MASK 0x0080000000000000 817 818 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 819 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 820 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 821 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 822 823 #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 824 #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 825 #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 826 #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff 827 828 #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 829 #define RX_MSDU_END_VLAN_STAG_CI_LSB 16 830 #define RX_MSDU_END_VLAN_STAG_CI_MSB 31 831 #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 832 833 #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 834 #define RX_MSDU_END_PEER_META_DATA_LSB 32 835 #define RX_MSDU_END_PEER_META_DATA_MSB 63 836 #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 837 838 #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 839 #define RX_MSDU_END_USER_RSSI_LSB 0 840 #define RX_MSDU_END_USER_RSSI_MSB 7 841 #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff 842 843 #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 844 #define RX_MSDU_END_PKT_TYPE_LSB 8 845 #define RX_MSDU_END_PKT_TYPE_MSB 11 846 #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 847 848 #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 849 #define RX_MSDU_END_SGI_LSB 12 850 #define RX_MSDU_END_SGI_MSB 13 851 #define RX_MSDU_END_SGI_MASK 0x0000000000003000 852 853 #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 854 #define RX_MSDU_END_RATE_MCS_LSB 14 855 #define RX_MSDU_END_RATE_MCS_MSB 17 856 #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 857 858 #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 859 #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 860 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 861 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 862 863 #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 864 #define RX_MSDU_END_RECEPTION_TYPE_LSB 21 865 #define RX_MSDU_END_RECEPTION_TYPE_MSB 23 866 #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 867 868 #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 869 #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 870 #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 871 #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 872 873 #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 874 #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 875 #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 876 #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 877 878 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 879 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 880 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 881 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 882 883 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 884 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 885 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 886 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff 887 888 #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 889 #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 890 #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 891 #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 892 893 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 894 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 895 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 896 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 897 898 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 899 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 900 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 901 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 902 903 #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 904 #define RX_MSDU_END_RESERVED_28A_LSB 0 905 #define RX_MSDU_END_RESERVED_28A_MSB 15 906 #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff 907 908 #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 909 #define RX_MSDU_END_SA_15_0_LSB 16 910 #define RX_MSDU_END_SA_15_0_MSB 31 911 #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 912 913 #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 914 #define RX_MSDU_END_SA_47_16_LSB 32 915 #define RX_MSDU_END_SA_47_16_MSB 63 916 #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 917 918 #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 919 #define RX_MSDU_END_FIRST_MPDU_LSB 0 920 #define RX_MSDU_END_FIRST_MPDU_MSB 0 921 #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 922 923 #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 924 #define RX_MSDU_END_RESERVED_30A_LSB 1 925 #define RX_MSDU_END_RESERVED_30A_MSB 1 926 #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 927 928 #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 929 #define RX_MSDU_END_MCAST_BCAST_LSB 2 930 #define RX_MSDU_END_MCAST_BCAST_MSB 2 931 #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 932 933 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 934 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 935 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 936 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 937 938 #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 939 #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 940 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 941 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 942 943 #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 944 #define RX_MSDU_END_POWER_MGMT_LSB 5 945 #define RX_MSDU_END_POWER_MGMT_MSB 5 946 #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 947 948 #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 949 #define RX_MSDU_END_NON_QOS_LSB 6 950 #define RX_MSDU_END_NON_QOS_MSB 6 951 #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 952 953 #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 954 #define RX_MSDU_END_NULL_DATA_LSB 7 955 #define RX_MSDU_END_NULL_DATA_MSB 7 956 #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 957 958 #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 959 #define RX_MSDU_END_MGMT_TYPE_LSB 8 960 #define RX_MSDU_END_MGMT_TYPE_MSB 8 961 #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 962 963 #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 964 #define RX_MSDU_END_CTRL_TYPE_LSB 9 965 #define RX_MSDU_END_CTRL_TYPE_MSB 9 966 #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 967 968 #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 969 #define RX_MSDU_END_MORE_DATA_LSB 10 970 #define RX_MSDU_END_MORE_DATA_MSB 10 971 #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 972 973 #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 974 #define RX_MSDU_END_EOSP_LSB 11 975 #define RX_MSDU_END_EOSP_MSB 11 976 #define RX_MSDU_END_EOSP_MASK 0x0000000000000800 977 978 #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 979 #define RX_MSDU_END_A_MSDU_ERROR_LSB 12 980 #define RX_MSDU_END_A_MSDU_ERROR_MSB 12 981 #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 982 983 #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 984 #define RX_MSDU_END_RESERVED_30B_LSB 13 985 #define RX_MSDU_END_RESERVED_30B_MSB 13 986 #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 987 988 #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 989 #define RX_MSDU_END_ORDER_LSB 14 990 #define RX_MSDU_END_ORDER_MSB 14 991 #define RX_MSDU_END_ORDER_MASK 0x0000000000004000 992 993 #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 994 #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 995 #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 996 #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 997 998 #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 999 #define RX_MSDU_END_OVERFLOW_ERR_LSB 16 1000 #define RX_MSDU_END_OVERFLOW_ERR_MSB 16 1001 #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 1002 1003 #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 1004 #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 1005 #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 1006 #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 1007 1008 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 1009 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 1010 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 1011 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 1012 1013 #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 1014 #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 1015 #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 1016 #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 1017 1018 #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 1019 #define RX_MSDU_END_SA_IDX_INVALID_LSB 20 1020 #define RX_MSDU_END_SA_IDX_INVALID_MSB 20 1021 #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 1022 1023 #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 1024 #define RX_MSDU_END_DA_IDX_INVALID_LSB 21 1025 #define RX_MSDU_END_DA_IDX_INVALID_MSB 21 1026 #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 1027 1028 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 1029 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 1030 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 1031 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 1032 1033 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 1034 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 1035 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 1036 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 1037 1038 #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 1039 #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 1040 #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 1041 #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 1042 1043 #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 1044 #define RX_MSDU_END_DIRECTED_LSB 25 1045 #define RX_MSDU_END_DIRECTED_MSB 25 1046 #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 1047 1048 #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 1049 #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 1050 #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 1051 #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 1052 1053 #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 1054 #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 1055 #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 1056 #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 1057 1058 #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 1059 #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 1060 #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 1061 #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 1062 1063 #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 1064 #define RX_MSDU_END_DECRYPT_ERR_LSB 29 1065 #define RX_MSDU_END_DECRYPT_ERR_MSB 29 1066 #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 1067 1068 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 1069 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 1070 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 1071 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 1072 1073 #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 1074 #define RX_MSDU_END_FCS_ERR_LSB 31 1075 #define RX_MSDU_END_FCS_ERR_MSB 31 1076 #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 1077 1078 #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 1079 #define RX_MSDU_END_RESERVED_31A_LSB 32 1080 #define RX_MSDU_END_RESERVED_31A_MSB 41 1081 #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 1082 1083 #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 1084 #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 1085 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 1086 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 1087 1088 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 1089 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 1090 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 1091 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 1092 1093 #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 1094 #define RX_MSDU_END_RESERVED_31B_LSB 46 1095 #define RX_MSDU_END_RESERVED_31B_MSB 62 1096 #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 1097 1098 #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 1099 #define RX_MSDU_END_MSDU_DONE_LSB 63 1100 #define RX_MSDU_END_MSDU_DONE_MSB 63 1101 #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 1102 1103 #endif 1104