1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_PPDU_END_USER_STATS_H_ 23 #define _RX_PPDU_END_USER_STATS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rx_rxpcu_classification_overview.h" 28 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 24 29 30 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 12 31 32 struct rx_ppdu_end_user_stats { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct rx_rxpcu_classification_overview rxpcu_classification_details; 35 uint32_t sta_full_aid : 13, 36 mcs : 4, 37 nss : 3, 38 expected_response_ack_or_ba : 1, 39 reserved_1a : 11; 40 uint32_t sw_peer_id : 16, 41 mpdu_cnt_fcs_err : 11, 42 sw2rxdma0_buf_source_used : 1, 43 fw2rxdma_pmac0_buf_source_used : 1, 44 sw2rxdma1_buf_source_used : 1, 45 sw2rxdma_exception_buf_source_used : 1, 46 fw2rxdma_pmac1_buf_source_used : 1; 47 uint32_t mpdu_cnt_fcs_ok : 11, 48 frame_control_info_valid : 1, 49 qos_control_info_valid : 1, 50 ht_control_info_valid : 1, 51 data_sequence_control_info_valid : 1, 52 ht_control_info_null_valid : 1, 53 rxdma2fw_pmac1_ring_used : 1, 54 rxdma2reo_ring_used : 1, 55 rxdma2fw_pmac0_ring_used : 1, 56 rxdma2sw_ring_used : 1, 57 rxdma_release_ring_used : 1, 58 ht_control_field_pkt_type : 4, 59 rxdma2reo_remote0_ring_used : 1, 60 rxdma2reo_remote1_ring_used : 1, 61 reserved_3b : 5; 62 uint32_t ast_index : 16, 63 frame_control_field : 16; 64 uint32_t first_data_seq_ctrl : 16, 65 qos_control_field : 16; 66 uint32_t ht_control_field : 32; 67 uint32_t fcs_ok_bitmap_31_0 : 32; 68 uint32_t fcs_ok_bitmap_63_32 : 32; 69 uint32_t udp_msdu_count : 16, 70 tcp_msdu_count : 16; 71 uint32_t other_msdu_count : 16, 72 tcp_ack_msdu_count : 16; 73 uint32_t sw_response_reference_ptr : 32; 74 uint32_t received_qos_data_tid_bitmap : 16, 75 received_qos_data_tid_eosp_bitmap : 16; 76 uint32_t qosctrl_15_8_tid0 : 8, 77 qosctrl_15_8_tid1 : 8, 78 qosctrl_15_8_tid2 : 8, 79 qosctrl_15_8_tid3 : 8; 80 uint32_t qosctrl_15_8_tid4 : 8, 81 qosctrl_15_8_tid5 : 8, 82 qosctrl_15_8_tid6 : 8, 83 qosctrl_15_8_tid7 : 8; 84 uint32_t qosctrl_15_8_tid8 : 8, 85 qosctrl_15_8_tid9 : 8, 86 qosctrl_15_8_tid10 : 8, 87 qosctrl_15_8_tid11 : 8; 88 uint32_t qosctrl_15_8_tid12 : 8, 89 qosctrl_15_8_tid13 : 8, 90 qosctrl_15_8_tid14 : 8, 91 qosctrl_15_8_tid15 : 8; 92 uint32_t mpdu_ok_byte_count : 25, 93 ampdu_delim_ok_count_6_0 : 7; 94 uint32_t ampdu_delim_err_count : 25, 95 ampdu_delim_ok_count_13_7 : 7; 96 uint32_t mpdu_err_byte_count : 25, 97 ampdu_delim_ok_count_20_14 : 7; 98 uint32_t non_consecutive_delimiter_err : 16, 99 retried_msdu_count : 16; 100 uint32_t ht_control_null_field : 32; 101 uint32_t sw_response_reference_ptr_ext : 32; 102 uint32_t corrupted_due_to_fifo_delay : 1, 103 frame_control_info_null_valid : 1, 104 frame_control_field_null : 16, 105 retried_mpdu_count : 11, 106 reserved_23a : 3; 107 #else 108 struct rx_rxpcu_classification_overview rxpcu_classification_details; 109 uint32_t reserved_1a : 11, 110 expected_response_ack_or_ba : 1, 111 nss : 3, 112 mcs : 4, 113 sta_full_aid : 13; 114 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 115 sw2rxdma_exception_buf_source_used : 1, 116 sw2rxdma1_buf_source_used : 1, 117 fw2rxdma_pmac0_buf_source_used : 1, 118 sw2rxdma0_buf_source_used : 1, 119 mpdu_cnt_fcs_err : 11, 120 sw_peer_id : 16; 121 uint32_t reserved_3b : 5, 122 rxdma2reo_remote1_ring_used : 1, 123 rxdma2reo_remote0_ring_used : 1, 124 ht_control_field_pkt_type : 4, 125 rxdma_release_ring_used : 1, 126 rxdma2sw_ring_used : 1, 127 rxdma2fw_pmac0_ring_used : 1, 128 rxdma2reo_ring_used : 1, 129 rxdma2fw_pmac1_ring_used : 1, 130 ht_control_info_null_valid : 1, 131 data_sequence_control_info_valid : 1, 132 ht_control_info_valid : 1, 133 qos_control_info_valid : 1, 134 frame_control_info_valid : 1, 135 mpdu_cnt_fcs_ok : 11; 136 uint32_t frame_control_field : 16, 137 ast_index : 16; 138 uint32_t qos_control_field : 16, 139 first_data_seq_ctrl : 16; 140 uint32_t ht_control_field : 32; 141 uint32_t fcs_ok_bitmap_31_0 : 32; 142 uint32_t fcs_ok_bitmap_63_32 : 32; 143 uint32_t tcp_msdu_count : 16, 144 udp_msdu_count : 16; 145 uint32_t tcp_ack_msdu_count : 16, 146 other_msdu_count : 16; 147 uint32_t sw_response_reference_ptr : 32; 148 uint32_t received_qos_data_tid_eosp_bitmap : 16, 149 received_qos_data_tid_bitmap : 16; 150 uint32_t qosctrl_15_8_tid3 : 8, 151 qosctrl_15_8_tid2 : 8, 152 qosctrl_15_8_tid1 : 8, 153 qosctrl_15_8_tid0 : 8; 154 uint32_t qosctrl_15_8_tid7 : 8, 155 qosctrl_15_8_tid6 : 8, 156 qosctrl_15_8_tid5 : 8, 157 qosctrl_15_8_tid4 : 8; 158 uint32_t qosctrl_15_8_tid11 : 8, 159 qosctrl_15_8_tid10 : 8, 160 qosctrl_15_8_tid9 : 8, 161 qosctrl_15_8_tid8 : 8; 162 uint32_t qosctrl_15_8_tid15 : 8, 163 qosctrl_15_8_tid14 : 8, 164 qosctrl_15_8_tid13 : 8, 165 qosctrl_15_8_tid12 : 8; 166 uint32_t ampdu_delim_ok_count_6_0 : 7, 167 mpdu_ok_byte_count : 25; 168 uint32_t ampdu_delim_ok_count_13_7 : 7, 169 ampdu_delim_err_count : 25; 170 uint32_t ampdu_delim_ok_count_20_14 : 7, 171 mpdu_err_byte_count : 25; 172 uint32_t retried_msdu_count : 16, 173 non_consecutive_delimiter_err : 16; 174 uint32_t ht_control_null_field : 32; 175 uint32_t sw_response_reference_ptr_ext : 32; 176 uint32_t reserved_23a : 3, 177 retried_mpdu_count : 11, 178 frame_control_field_null : 16, 179 frame_control_info_null_valid : 1, 180 corrupted_due_to_fifo_delay : 1; 181 #endif 182 }; 183 184 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 185 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 186 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 187 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 188 189 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 190 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 191 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 192 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 193 194 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 195 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 196 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 197 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 198 199 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 200 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 201 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 202 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 203 204 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 205 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 206 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 207 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 208 209 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 210 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 211 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 212 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 213 214 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 215 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 216 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 217 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 218 219 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 220 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 221 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 222 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 223 224 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 225 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 226 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 227 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 228 229 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 230 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 231 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 232 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 233 234 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 235 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 236 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 237 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 238 239 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 240 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 241 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 242 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 243 244 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 245 #define RX_PPDU_END_USER_STATS_MCS_LSB 45 246 #define RX_PPDU_END_USER_STATS_MCS_MSB 48 247 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 248 249 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 250 #define RX_PPDU_END_USER_STATS_NSS_LSB 49 251 #define RX_PPDU_END_USER_STATS_NSS_MSB 51 252 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 253 254 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 255 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 256 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 257 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 258 259 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 260 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 261 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 262 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 263 264 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 265 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 266 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 267 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff 268 269 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 270 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 271 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 272 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 273 274 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 275 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 276 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 277 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 278 279 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 280 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 281 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 282 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 283 284 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 285 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 286 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 287 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 288 289 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 290 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 291 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 292 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 293 294 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 295 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 296 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 297 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 298 299 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 300 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 301 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 302 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 303 304 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 305 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 306 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 307 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 308 309 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 310 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 311 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 312 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 313 314 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 315 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 316 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 317 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 318 319 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 320 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 321 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 322 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 323 324 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 325 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 326 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 327 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 328 329 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 330 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 331 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 332 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 333 334 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 335 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 336 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 337 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 338 339 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 340 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 341 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 342 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 343 344 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 345 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 346 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 347 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 348 349 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 350 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 351 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 352 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 353 354 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 355 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 356 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 357 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 358 359 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 360 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 361 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 362 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 363 364 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 365 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 366 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 367 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 368 369 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 370 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 371 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 372 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 373 374 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 375 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 376 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 377 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff 378 379 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 380 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 381 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 382 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 383 384 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 385 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 386 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 387 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 388 389 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 390 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 391 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 392 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 393 394 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 395 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 396 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 397 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 398 399 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 400 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 401 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 402 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 403 404 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 405 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 406 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 407 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff 408 409 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 410 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 411 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 412 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 413 414 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 415 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 416 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 417 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 418 419 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 420 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 421 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 422 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff 423 424 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 425 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 426 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 427 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 428 429 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 430 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 431 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 432 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 433 434 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 435 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 436 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 437 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff 438 439 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 440 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 441 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 442 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 443 444 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 445 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 446 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 447 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 448 449 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 450 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 451 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 452 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 453 454 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 455 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 456 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 457 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 458 459 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 460 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 461 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 462 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 463 464 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 465 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 466 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 467 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff 468 469 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 470 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 471 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 472 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 473 474 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 475 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 476 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 477 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 478 479 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 480 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 481 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 482 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 483 484 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 485 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 486 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 487 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 488 489 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 490 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 491 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 492 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 493 494 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 495 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 496 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 497 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 498 499 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 500 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 501 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 502 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 503 504 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 505 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 506 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 507 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff 508 509 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 510 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 511 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 512 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 513 514 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 515 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 516 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 517 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 518 519 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 520 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 521 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 522 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 523 524 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 525 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 526 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 527 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 528 529 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 530 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 531 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 532 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 533 534 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 535 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 536 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 537 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff 538 539 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 540 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 541 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 542 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 543 544 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 545 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 546 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 547 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 548 549 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 550 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 551 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 552 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 553 554 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 555 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 556 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 557 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff 558 559 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 560 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 561 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 562 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 563 564 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 565 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 566 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 567 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 568 569 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 570 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 571 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 572 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff 573 574 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 575 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 576 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 577 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 578 579 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 580 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 581 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 582 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 583 584 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 585 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 586 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 587 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 588 589 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 590 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 591 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 592 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 593 594 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 595 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 596 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 597 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 598 599 #endif 600