1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_PPDU_START_H_ 23 #define _RX_PPDU_START_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_PPDU_START 6 28 29 #define NUM_OF_QWORDS_RX_PPDU_START 3 30 31 struct rx_ppdu_start { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 uint32_t phy_ppdu_id : 16, 34 preamble_time_to_rxframe : 8, 35 reserved_0a : 8; 36 uint32_t sw_phy_meta_data : 32; 37 uint32_t ppdu_start_timestamp_31_0 : 32; 38 uint32_t ppdu_start_timestamp_63_32 : 32; 39 uint32_t rxframe_assert_timestamp : 32; 40 uint32_t tlv64_padding : 32; 41 #else 42 uint32_t reserved_0a : 8, 43 preamble_time_to_rxframe : 8, 44 phy_ppdu_id : 16; 45 uint32_t sw_phy_meta_data : 32; 46 uint32_t ppdu_start_timestamp_31_0 : 32; 47 uint32_t ppdu_start_timestamp_63_32 : 32; 48 uint32_t rxframe_assert_timestamp : 32; 49 uint32_t tlv64_padding : 32; 50 #endif 51 }; 52 53 #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 54 #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 55 #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 56 #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 57 58 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 59 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 60 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 61 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 62 63 #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 64 #define RX_PPDU_START_RESERVED_0A_LSB 24 65 #define RX_PPDU_START_RESERVED_0A_MSB 31 66 #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 67 68 #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 69 #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 70 #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 71 #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 72 73 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 74 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 75 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 76 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 77 78 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 79 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 80 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 81 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 82 83 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 84 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 85 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 86 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 87 88 #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 89 #define RX_PPDU_START_TLV64_PADDING_LSB 32 90 #define RX_PPDU_START_TLV64_PADDING_MSB 63 91 #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 92 93 #endif 94