1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_REO_QUEUE_H_ 23 #define _RX_REO_QUEUE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_descriptor_header.h" 28 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 29 30 struct rx_reo_queue { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_descriptor_header descriptor_header; 33 uint32_t receive_queue_number : 16, 34 reserved_1b : 16; 35 uint32_t vld : 1, 36 associated_link_descriptor_counter : 2, 37 disable_duplicate_detection : 1, 38 soft_reorder_enable : 1, 39 ac : 2, 40 bar : 1, 41 rty : 1, 42 chk_2k_mode : 1, 43 oor_mode : 1, 44 ba_window_size : 10, 45 pn_check_needed : 1, 46 pn_shall_be_even : 1, 47 pn_shall_be_uneven : 1, 48 pn_handling_enable : 1, 49 pn_size : 2, 50 ignore_ampdu_flag : 1, 51 reserved_2b : 4; 52 uint32_t svld : 1, 53 ssn : 12, 54 current_index : 10, 55 seq_2k_error_detected_flag : 1, 56 pn_error_detected_flag : 1, 57 reserved_3a : 6, 58 pn_valid : 1; 59 uint32_t pn_31_0 : 32; 60 uint32_t pn_63_32 : 32; 61 uint32_t pn_95_64 : 32; 62 uint32_t pn_127_96 : 32; 63 uint32_t last_rx_enqueue_timestamp : 32; 64 uint32_t last_rx_dequeue_timestamp : 32; 65 uint32_t ptr_to_next_aging_queue_31_0 : 32; 66 uint32_t ptr_to_next_aging_queue_39_32 : 8, 67 reserved_11a : 24; 68 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 69 uint32_t ptr_to_previous_aging_queue_39_32 : 8, 70 statistics_counter_index : 6, 71 reserved_13a : 18; 72 uint32_t rx_bitmap_31_0 : 32; 73 uint32_t rx_bitmap_63_32 : 32; 74 uint32_t rx_bitmap_95_64 : 32; 75 uint32_t rx_bitmap_127_96 : 32; 76 uint32_t rx_bitmap_159_128 : 32; 77 uint32_t rx_bitmap_191_160 : 32; 78 uint32_t rx_bitmap_223_192 : 32; 79 uint32_t rx_bitmap_255_224 : 32; 80 uint32_t rx_bitmap_287_256 : 32; 81 uint32_t current_mpdu_count : 7, 82 current_msdu_count : 25; 83 uint32_t last_sn_reg_index : 4, 84 timeout_count : 6, 85 forward_due_to_bar_count : 6, 86 duplicate_count : 16; 87 uint32_t frames_in_order_count : 24, 88 bar_received_count : 8; 89 uint32_t mpdu_frames_processed_count : 32; 90 uint32_t msdu_frames_processed_count : 32; 91 uint32_t total_processed_byte_count : 32; 92 uint32_t late_receive_mpdu_count : 12, 93 window_jump_2k : 4, 94 hole_count : 16; 95 uint32_t aging_drop_mpdu_count : 16, 96 aging_drop_interval : 8, 97 reserved_30 : 8; 98 uint32_t reserved_31 : 32; 99 #else 100 struct uniform_descriptor_header descriptor_header; 101 uint32_t reserved_1b : 16, 102 receive_queue_number : 16; 103 uint32_t reserved_2b : 4, 104 ignore_ampdu_flag : 1, 105 pn_size : 2, 106 pn_handling_enable : 1, 107 pn_shall_be_uneven : 1, 108 pn_shall_be_even : 1, 109 pn_check_needed : 1, 110 ba_window_size : 10, 111 oor_mode : 1, 112 chk_2k_mode : 1, 113 rty : 1, 114 bar : 1, 115 ac : 2, 116 soft_reorder_enable : 1, 117 disable_duplicate_detection : 1, 118 associated_link_descriptor_counter : 2, 119 vld : 1; 120 uint32_t pn_valid : 1, 121 reserved_3a : 6, 122 pn_error_detected_flag : 1, 123 seq_2k_error_detected_flag : 1, 124 current_index : 10, 125 ssn : 12, 126 svld : 1; 127 uint32_t pn_31_0 : 32; 128 uint32_t pn_63_32 : 32; 129 uint32_t pn_95_64 : 32; 130 uint32_t pn_127_96 : 32; 131 uint32_t last_rx_enqueue_timestamp : 32; 132 uint32_t last_rx_dequeue_timestamp : 32; 133 uint32_t ptr_to_next_aging_queue_31_0 : 32; 134 uint32_t reserved_11a : 24, 135 ptr_to_next_aging_queue_39_32 : 8; 136 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 137 uint32_t reserved_13a : 18, 138 statistics_counter_index : 6, 139 ptr_to_previous_aging_queue_39_32 : 8; 140 uint32_t rx_bitmap_31_0 : 32; 141 uint32_t rx_bitmap_63_32 : 32; 142 uint32_t rx_bitmap_95_64 : 32; 143 uint32_t rx_bitmap_127_96 : 32; 144 uint32_t rx_bitmap_159_128 : 32; 145 uint32_t rx_bitmap_191_160 : 32; 146 uint32_t rx_bitmap_223_192 : 32; 147 uint32_t rx_bitmap_255_224 : 32; 148 uint32_t rx_bitmap_287_256 : 32; 149 uint32_t current_msdu_count : 25, 150 current_mpdu_count : 7; 151 uint32_t duplicate_count : 16, 152 forward_due_to_bar_count : 6, 153 timeout_count : 6, 154 last_sn_reg_index : 4; 155 uint32_t bar_received_count : 8, 156 frames_in_order_count : 24; 157 uint32_t mpdu_frames_processed_count : 32; 158 uint32_t msdu_frames_processed_count : 32; 159 uint32_t total_processed_byte_count : 32; 160 uint32_t hole_count : 16, 161 window_jump_2k : 4, 162 late_receive_mpdu_count : 12; 163 uint32_t reserved_30 : 8, 164 aging_drop_interval : 8, 165 aging_drop_mpdu_count : 16; 166 uint32_t reserved_31 : 32; 167 #endif 168 }; 169 170 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 171 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 172 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 173 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 174 175 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 176 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 177 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 178 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 179 180 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 181 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 182 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 183 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 184 185 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 186 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 187 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 188 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 189 190 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 191 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 192 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 193 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 194 195 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 196 #define RX_REO_QUEUE_VLD_LSB 0 197 #define RX_REO_QUEUE_VLD_MSB 0 198 #define RX_REO_QUEUE_VLD_MASK 0x00000001 199 200 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 201 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 202 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 203 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 204 205 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 206 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 207 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 208 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 209 210 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 211 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 212 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 213 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 214 215 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 216 #define RX_REO_QUEUE_AC_LSB 5 217 #define RX_REO_QUEUE_AC_MSB 6 218 #define RX_REO_QUEUE_AC_MASK 0x00000060 219 220 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 221 #define RX_REO_QUEUE_BAR_LSB 7 222 #define RX_REO_QUEUE_BAR_MSB 7 223 #define RX_REO_QUEUE_BAR_MASK 0x00000080 224 225 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 226 #define RX_REO_QUEUE_RTY_LSB 8 227 #define RX_REO_QUEUE_RTY_MSB 8 228 #define RX_REO_QUEUE_RTY_MASK 0x00000100 229 230 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 231 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 232 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 233 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 234 235 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 236 #define RX_REO_QUEUE_OOR_MODE_LSB 10 237 #define RX_REO_QUEUE_OOR_MODE_MSB 10 238 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 239 240 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 241 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 242 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 243 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 244 245 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 246 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 247 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 248 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 249 250 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 251 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 252 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 253 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 254 255 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 256 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 257 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 258 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 259 260 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 261 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 262 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 263 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 264 265 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 266 #define RX_REO_QUEUE_PN_SIZE_LSB 25 267 #define RX_REO_QUEUE_PN_SIZE_MSB 26 268 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 269 270 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 271 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 272 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 273 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 274 275 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 276 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 277 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 278 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 279 280 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 281 #define RX_REO_QUEUE_SVLD_LSB 0 282 #define RX_REO_QUEUE_SVLD_MSB 0 283 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 284 285 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 286 #define RX_REO_QUEUE_SSN_LSB 1 287 #define RX_REO_QUEUE_SSN_MSB 12 288 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 289 290 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 291 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 292 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 293 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 294 295 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 296 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 297 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 298 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 299 300 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 301 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 302 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 303 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 304 305 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 306 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 307 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 308 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 309 310 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 311 #define RX_REO_QUEUE_PN_VALID_LSB 31 312 #define RX_REO_QUEUE_PN_VALID_MSB 31 313 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 314 315 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 316 #define RX_REO_QUEUE_PN_31_0_LSB 0 317 #define RX_REO_QUEUE_PN_31_0_MSB 31 318 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 319 320 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 321 #define RX_REO_QUEUE_PN_63_32_LSB 0 322 #define RX_REO_QUEUE_PN_63_32_MSB 31 323 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 324 325 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 326 #define RX_REO_QUEUE_PN_95_64_LSB 0 327 #define RX_REO_QUEUE_PN_95_64_MSB 31 328 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 329 330 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 331 #define RX_REO_QUEUE_PN_127_96_LSB 0 332 #define RX_REO_QUEUE_PN_127_96_MSB 31 333 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 334 335 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 336 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 337 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 338 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 339 340 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 341 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 342 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 343 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 344 345 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 346 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 347 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 348 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 349 350 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 351 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 352 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 353 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 354 355 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 356 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 357 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 358 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 359 360 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 361 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 362 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 363 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 364 365 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 366 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 367 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 368 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 369 370 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 371 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 372 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 373 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 374 375 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 376 #define RX_REO_QUEUE_RESERVED_13A_LSB 14 377 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 378 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 379 380 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 381 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 382 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 383 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 384 385 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 386 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 387 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 388 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 389 390 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 391 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 392 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 393 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 394 395 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 396 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 397 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 398 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 399 400 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 401 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 402 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 403 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 404 405 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 406 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 407 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 408 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 409 410 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 411 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 412 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 413 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 414 415 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 416 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 417 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 418 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 419 420 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 421 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 422 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 423 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 424 425 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 426 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 427 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 428 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 429 430 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 431 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 432 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 433 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 434 435 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 436 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 437 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 438 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 439 440 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 441 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 442 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 443 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 444 445 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 446 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 447 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 448 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 449 450 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 451 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 452 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 453 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 454 455 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 456 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 457 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 458 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 459 460 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 461 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 462 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 463 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 464 465 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 466 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 467 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 468 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 469 470 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 471 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 472 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 473 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 474 475 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 476 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 477 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 478 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 479 480 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 481 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 482 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 483 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 484 485 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 486 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 487 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 488 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 489 490 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 491 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 492 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 493 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 494 495 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 496 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 497 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 498 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff 499 500 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 501 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 502 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 503 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 504 505 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 506 #define RX_REO_QUEUE_RESERVED_30_LSB 24 507 #define RX_REO_QUEUE_RESERVED_30_MSB 31 508 #define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 509 510 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 511 #define RX_REO_QUEUE_RESERVED_31_LSB 0 512 #define RX_REO_QUEUE_RESERVED_31_MSB 31 513 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 514 515 #endif 516