1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _RX_RESPONSE_REQUIRED_INFO_H_ 21 #define _RX_RESPONSE_REQUIRED_INFO_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "mlo_sta_id_details.h" 26 #define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 27 28 #define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 29 30 struct rx_response_required_info { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t phy_ppdu_id : 16, 33 su_or_uplink_mu_reception : 1, 34 trigger_frame_received : 1, 35 __reserved_g_0012 : 2, 36 tb___reserved_g_0005_response_required : 2, 37 mac_security : 1, 38 filter_pass_monitor_ovrd : 1, 39 ast_search_incomplete : 1, 40 r2r_end_status_to_follow : 1, 41 reserved_0a : 2, 42 three_or_more_type_subtypes : 1, 43 wait_sifs_config_valid : 1, 44 wait_sifs : 2; 45 uint32_t general_frame_control : 16, 46 second_frame_control : 16; 47 uint32_t duration : 16, 48 pkt_type : 4, 49 dot11ax_su_extended : 1, 50 rate_mcs : 4, 51 sgi : 2, 52 stbc : 1, 53 ldpc : 1, 54 ampdu : 1, 55 vht_ack : 1, 56 rts_ta_grp_bit : 1; 57 uint32_t ctrl_frame_soliciting_resp : 1, 58 ast_fail_for_dot11ax_su_ext : 1, 59 service_dynamic : 1, 60 m_pkt : 1, 61 sta_partial_aid : 12, 62 group_id : 6, 63 ctrl_resp_pwr_mgmt : 1, 64 response_indication : 2, 65 ndp_indication : 1, 66 ndp_frame_type : 3, 67 second_frame_control_valid : 1, 68 reserved_3a : 2; 69 uint32_t ack_id : 16, 70 ack_id_ext : 10, 71 agc_cbw : 3, 72 service_cbw : 3; 73 uint32_t response_sta_count : 7, 74 reserved : 4, 75 ht_vht_sig_cbw : 3, 76 cts_cbw : 3, 77 response_ack_count : 7, 78 response_assoc_ack_count : 7, 79 txop_duration_all_ones : 1; 80 uint32_t response_ba32_count : 7, 81 response_ba64_count : 7, 82 response_ba128_count : 7, 83 response_ba256_count : 7, 84 multi_tid : 1, 85 sw_response_tlv_from_crypto : 1, 86 dot11ax_dl_ul_flag : 1, 87 reserved_6a : 1; 88 uint32_t sw_response_frame_length : 16, 89 response_ba512_count : 7, 90 response_ba1024_count : 7, 91 reserved_7a : 2; 92 uint32_t addr1_31_0 : 32; 93 uint32_t addr1_47_32 : 16, 94 addr2_15_0 : 16; 95 uint32_t addr2_47_16 : 32; 96 uint32_t dot11ax_received_format_indication : 1, 97 dot11ax_received_dl_ul_flag : 1, 98 dot11ax_received_bss_color_id : 6, 99 dot11ax_received_spatial_reuse : 4, 100 dot11ax_received_cp_size : 2, 101 dot11ax_received_ltf_size : 2, 102 dot11ax_received_coding : 1, 103 dot11ax_received_dcm : 1, 104 dot11ax_received_doppler_indication : 1, 105 dot11ax_received_ext_ru_size : 4, 106 ftm_fields_valid : 1, 107 ftm_pe_nss : 3, 108 ftm_pe_ltf_size : 2, 109 ftm_pe_content : 1, 110 ftm_chain_csd_en : 1, 111 ftm_pe_chain_csd_en : 1; 112 uint32_t dot11ax_response_rate_source : 8, 113 dot11ax_ext_response_rate_source : 8, 114 sw_peer_id : 16; 115 uint32_t dot11be_puncture_bitmap : 16, 116 dot11be_response : 1, 117 punctured_response : 1, 118 eht_duplicate_mode : 2, 119 force_extra_symbol : 1, 120 reserved_13a : 5, 121 u_sig_puncture_pattern_encoding : 6; 122 struct mlo_sta_id_details mlo_sta_id_details_rx; 123 uint16_t he_a_control_response_time : 12, 124 reserved_after_struct16 : 4; 125 uint32_t tlv64_padding : 32; 126 #else 127 uint32_t wait_sifs : 2, 128 wait_sifs_config_valid : 1, 129 three_or_more_type_subtypes : 1, 130 reserved_0a : 2, 131 r2r_end_status_to_follow : 1, 132 ast_search_incomplete : 1, 133 filter_pass_monitor_ovrd : 1, 134 mac_security : 1, 135 tb___reserved_g_0005_response_required : 2, 136 __reserved_g_0012 : 2, 137 trigger_frame_received : 1, 138 su_or_uplink_mu_reception : 1, 139 phy_ppdu_id : 16; 140 uint32_t second_frame_control : 16, 141 general_frame_control : 16; 142 uint32_t rts_ta_grp_bit : 1, 143 vht_ack : 1, 144 ampdu : 1, 145 ldpc : 1, 146 stbc : 1, 147 sgi : 2, 148 rate_mcs : 4, 149 dot11ax_su_extended : 1, 150 pkt_type : 4, 151 duration : 16; 152 uint32_t reserved_3a : 2, 153 second_frame_control_valid : 1, 154 ndp_frame_type : 3, 155 ndp_indication : 1, 156 response_indication : 2, 157 ctrl_resp_pwr_mgmt : 1, 158 group_id : 6, 159 sta_partial_aid : 12, 160 m_pkt : 1, 161 service_dynamic : 1, 162 ast_fail_for_dot11ax_su_ext : 1, 163 ctrl_frame_soliciting_resp : 1; 164 uint32_t service_cbw : 3, 165 agc_cbw : 3, 166 ack_id_ext : 10, 167 ack_id : 16; 168 uint32_t txop_duration_all_ones : 1, 169 response_assoc_ack_count : 7, 170 response_ack_count : 7, 171 cts_cbw : 3, 172 ht_vht_sig_cbw : 3, 173 reserved : 4, 174 response_sta_count : 7; 175 uint32_t reserved_6a : 1, 176 dot11ax_dl_ul_flag : 1, 177 sw_response_tlv_from_crypto : 1, 178 multi_tid : 1, 179 response_ba256_count : 7, 180 response_ba128_count : 7, 181 response_ba64_count : 7, 182 response_ba32_count : 7; 183 uint32_t reserved_7a : 2, 184 response_ba1024_count : 7, 185 response_ba512_count : 7, 186 sw_response_frame_length : 16; 187 uint32_t addr1_31_0 : 32; 188 uint32_t addr2_15_0 : 16, 189 addr1_47_32 : 16; 190 uint32_t addr2_47_16 : 32; 191 uint32_t ftm_pe_chain_csd_en : 1, 192 ftm_chain_csd_en : 1, 193 ftm_pe_content : 1, 194 ftm_pe_ltf_size : 2, 195 ftm_pe_nss : 3, 196 ftm_fields_valid : 1, 197 dot11ax_received_ext_ru_size : 4, 198 dot11ax_received_doppler_indication : 1, 199 dot11ax_received_dcm : 1, 200 dot11ax_received_coding : 1, 201 dot11ax_received_ltf_size : 2, 202 dot11ax_received_cp_size : 2, 203 dot11ax_received_spatial_reuse : 4, 204 dot11ax_received_bss_color_id : 6, 205 dot11ax_received_dl_ul_flag : 1, 206 dot11ax_received_format_indication : 1; 207 uint32_t sw_peer_id : 16, 208 dot11ax_ext_response_rate_source : 8, 209 dot11ax_response_rate_source : 8; 210 uint32_t u_sig_puncture_pattern_encoding : 6, 211 reserved_13a : 5, 212 force_extra_symbol : 1, 213 eht_duplicate_mode : 2, 214 punctured_response : 1, 215 dot11be_response : 1, 216 dot11be_puncture_bitmap : 16; 217 uint32_t reserved_after_struct16 : 4, 218 he_a_control_response_time : 12; 219 struct mlo_sta_id_details mlo_sta_id_details_rx; 220 uint32_t tlv64_padding : 32; 221 #endif 222 }; 223 224 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 225 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 226 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 227 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff 228 229 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 230 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 231 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 232 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 233 234 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 235 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 236 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 237 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 238 239 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 240 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 241 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 242 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 243 244 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 245 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 246 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 247 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 248 249 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 250 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 251 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 252 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 253 254 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 255 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 256 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 257 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 258 259 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 260 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 261 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 262 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 263 264 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 265 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 266 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 267 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 268 269 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 270 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 271 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 272 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 273 274 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 275 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 276 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 277 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 278 279 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 280 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 281 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 282 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 283 284 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 285 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 286 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 287 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 288 289 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 290 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 291 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 292 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 293 294 #define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 295 #define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 296 #define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 297 #define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff 298 299 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 300 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 301 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 302 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 303 304 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 305 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 306 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 307 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 308 309 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 310 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 311 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 312 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 313 314 #define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 315 #define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 316 #define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 317 #define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 318 319 #define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 320 #define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 321 #define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 322 #define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 323 324 #define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 325 #define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 326 #define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 327 #define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 328 329 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 330 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 331 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 332 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 333 334 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 335 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 336 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 337 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 338 339 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 340 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 341 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 342 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 343 344 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 345 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 346 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 347 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 348 349 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 350 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 351 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 352 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 353 354 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 355 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 356 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 357 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 358 359 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 360 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 361 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 362 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 363 364 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 365 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 366 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 367 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 368 369 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 370 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 371 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 372 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 373 374 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 375 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 376 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 377 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 378 379 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 380 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 381 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 382 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 383 384 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 385 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 386 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 387 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 388 389 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 390 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 391 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 392 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 393 394 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 395 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 396 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 397 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 398 399 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 400 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 401 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 402 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 403 404 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 405 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 406 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 407 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff 408 409 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 410 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 411 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 412 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 413 414 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 415 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 416 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 417 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 418 419 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 420 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 421 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 422 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 423 424 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 425 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 426 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 427 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 428 429 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 430 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 431 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 432 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 433 434 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 435 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 436 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 437 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 438 439 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 440 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 441 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 442 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 443 444 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 445 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 446 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 447 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 448 449 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 450 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 451 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 452 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 453 454 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 455 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 456 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 457 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 458 459 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 460 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 461 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 462 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f 463 464 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 465 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 466 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 467 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 468 469 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 470 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 471 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 472 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 473 474 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 475 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 476 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 477 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 478 479 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 480 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 481 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 482 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 483 484 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 485 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 486 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 487 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 488 489 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 490 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 491 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 492 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 493 494 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 495 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 496 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 497 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 498 499 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 500 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 501 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 502 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 503 504 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 505 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 506 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 507 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 508 509 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 510 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 511 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 512 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 513 514 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 515 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 516 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 517 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 518 519 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 520 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 521 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 522 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff 523 524 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 525 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 526 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 527 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 528 529 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 530 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 531 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 532 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 533 534 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 535 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 536 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 537 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff 538 539 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 540 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 541 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 542 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 543 544 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 545 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 546 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 547 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 548 549 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 550 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 551 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 552 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 553 554 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 555 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 556 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 557 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 558 559 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 560 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 561 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 562 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 563 564 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 565 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 566 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 567 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 568 569 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 570 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 571 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 572 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 573 574 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 575 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 576 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 577 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 578 579 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 580 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 581 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 582 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 583 584 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 585 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 586 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 587 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 588 589 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 590 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 591 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 592 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 593 594 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 595 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 596 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 597 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 598 599 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 600 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 601 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 602 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 603 604 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 605 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 606 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 607 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 608 609 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 610 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 611 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 612 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 613 614 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 615 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 616 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 617 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 618 619 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 620 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 621 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 622 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff 623 624 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 625 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 626 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 627 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 628 629 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 630 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 631 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 632 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 633 634 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 635 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 636 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 637 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 638 639 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 640 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 641 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 642 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 643 644 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 645 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 646 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 647 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 648 649 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 650 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 651 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 652 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 653 654 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 655 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 656 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 657 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 658 659 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 660 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 661 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 662 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 663 664 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 665 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 666 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 667 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 668 669 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 670 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 671 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 672 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff 673 674 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 675 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 676 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 677 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 678 679 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 680 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 681 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 682 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 683 684 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 685 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 686 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 687 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 688 689 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 690 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 691 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 692 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 693 694 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 695 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 696 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 697 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 698 699 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 700 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 701 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 702 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 703 704 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 705 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 706 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 707 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 708 709 #endif 710