1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RXPCU_PPDU_END_INFO_H_ 23 #define _RXPCU_PPDU_END_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "phyrx_abort_request_info.h" 28 #include "macrx_abort_request_info.h" 29 #include "rxpcu_ppdu_end_layout_info.h" 30 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 31 32 #define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 33 34 struct rxpcu_ppdu_end_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t wb_timestamp_lower_32 : 32; 37 uint32_t wb_timestamp_upper_32 : 32; 38 uint32_t rx_antenna : 24, 39 tx_ht_vht_ack : 1, 40 unsupported_mu_nc : 1, 41 otp_txbf_disable : 1, 42 previous_tlv_corrupted : 1, 43 phyrx_abort_request_info_valid : 1, 44 macrx_abort_request_info_valid : 1, 45 reserved : 2; 46 uint32_t coex_bt_tx_from_start_of_rx : 1, 47 coex_bt_tx_after_start_of_rx : 1, 48 coex_wan_tx_from_start_of_rx : 1, 49 coex_wan_tx_after_start_of_rx : 1, 50 coex_wlan_tx_from_start_of_rx : 1, 51 coex_wlan_tx_after_start_of_rx : 1, 52 mpdu_delimiter_errors_seen : 1, 53 __reserved_g_0012 : 2, 54 dialog_token : 8, 55 follow_up_dialog_token : 8, 56 bb_captured_channel : 1, 57 bb_captured_reason : 3, 58 bb_captured_timeout : 1, 59 reserved_3 : 2; 60 uint32_t before_mpdu_count_passing_fcs : 10, 61 before_mpdu_count_failing_fcs : 10, 62 after_mpdu_count_passing_fcs : 10, 63 reserved_4 : 2; 64 uint32_t after_mpdu_count_failing_fcs : 10, 65 reserved_5 : 22; 66 uint32_t phy_timestamp_tx_lower_32 : 32; 67 uint32_t phy_timestamp_tx_upper_32 : 32; 68 uint32_t bb_length : 16, 69 bb_data : 1, 70 reserved_8 : 3, 71 first_bt_broadcast_status_details : 12; 72 uint32_t rx_ppdu_duration : 24, 73 reserved_9 : 8; 74 uint32_t ast_index : 16, 75 ast_index_valid : 1, 76 reserved_10 : 3, 77 second_bt_broadcast_status_details : 12; 78 struct phyrx_abort_request_info phyrx_abort_request_info_details; 79 struct macrx_abort_request_info macrx_abort_request_info_details; 80 uint16_t pre_bt_broadcast_status_details : 12, 81 reserved_12a : 4; 82 uint32_t non_qos_sn_info_valid : 1, 83 reserved_13a : 5, 84 non_qos_sn_highest : 12, 85 non_qos_sn_highest_retry_setting : 1, 86 non_qos_sn_lowest : 12, 87 non_qos_sn_lowest_retry_setting : 1; 88 uint32_t qos_sn_1_info_valid : 1, 89 reserved_14a : 1, 90 qos_sn_1_tid : 4, 91 qos_sn_1_highest : 12, 92 qos_sn_1_highest_retry_setting : 1, 93 qos_sn_1_lowest : 12, 94 qos_sn_1_lowest_retry_setting : 1; 95 uint32_t qos_sn_2_info_valid : 1, 96 reserved_15a : 1, 97 qos_sn_2_tid : 4, 98 qos_sn_2_highest : 12, 99 qos_sn_2_highest_retry_setting : 1, 100 qos_sn_2_lowest : 12, 101 qos_sn_2_lowest_retry_setting : 1; 102 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 103 uint32_t corrupted_due_to_fifo_delay : 1, 104 qos_sn_1_more_frag_state : 1, 105 qos_sn_1_frag_num_state : 4, 106 qos_sn_2_more_frag_state : 1, 107 qos_sn_2_frag_num_state : 4, 108 reserved_26a : 21; 109 uint32_t rx_ppdu_end_marker : 32; 110 #else 111 uint32_t wb_timestamp_lower_32 : 32; 112 uint32_t wb_timestamp_upper_32 : 32; 113 uint32_t reserved : 2, 114 macrx_abort_request_info_valid : 1, 115 phyrx_abort_request_info_valid : 1, 116 previous_tlv_corrupted : 1, 117 otp_txbf_disable : 1, 118 unsupported_mu_nc : 1, 119 tx_ht_vht_ack : 1, 120 rx_antenna : 24; 121 uint32_t reserved_3 : 2, 122 bb_captured_timeout : 1, 123 bb_captured_reason : 3, 124 bb_captured_channel : 1, 125 follow_up_dialog_token : 8, 126 dialog_token : 8, 127 __reserved_g_0012 : 2, 128 mpdu_delimiter_errors_seen : 1, 129 coex_wlan_tx_after_start_of_rx : 1, 130 coex_wlan_tx_from_start_of_rx : 1, 131 coex_wan_tx_after_start_of_rx : 1, 132 coex_wan_tx_from_start_of_rx : 1, 133 coex_bt_tx_after_start_of_rx : 1, 134 coex_bt_tx_from_start_of_rx : 1; 135 uint32_t reserved_4 : 2, 136 after_mpdu_count_passing_fcs : 10, 137 before_mpdu_count_failing_fcs : 10, 138 before_mpdu_count_passing_fcs : 10; 139 uint32_t reserved_5 : 22, 140 after_mpdu_count_failing_fcs : 10; 141 uint32_t phy_timestamp_tx_lower_32 : 32; 142 uint32_t phy_timestamp_tx_upper_32 : 32; 143 uint32_t first_bt_broadcast_status_details : 12, 144 reserved_8 : 3, 145 bb_data : 1, 146 bb_length : 16; 147 uint32_t reserved_9 : 8, 148 rx_ppdu_duration : 24; 149 uint32_t second_bt_broadcast_status_details : 12, 150 reserved_10 : 3, 151 ast_index_valid : 1, 152 ast_index : 16; 153 struct phyrx_abort_request_info phyrx_abort_request_info_details; 154 uint32_t reserved_12a : 4, 155 pre_bt_broadcast_status_details : 12; 156 struct macrx_abort_request_info macrx_abort_request_info_details; 157 uint32_t non_qos_sn_lowest_retry_setting : 1, 158 non_qos_sn_lowest : 12, 159 non_qos_sn_highest_retry_setting : 1, 160 non_qos_sn_highest : 12, 161 reserved_13a : 5, 162 non_qos_sn_info_valid : 1; 163 uint32_t qos_sn_1_lowest_retry_setting : 1, 164 qos_sn_1_lowest : 12, 165 qos_sn_1_highest_retry_setting : 1, 166 qos_sn_1_highest : 12, 167 qos_sn_1_tid : 4, 168 reserved_14a : 1, 169 qos_sn_1_info_valid : 1; 170 uint32_t qos_sn_2_lowest_retry_setting : 1, 171 qos_sn_2_lowest : 12, 172 qos_sn_2_highest_retry_setting : 1, 173 qos_sn_2_highest : 12, 174 qos_sn_2_tid : 4, 175 reserved_15a : 1, 176 qos_sn_2_info_valid : 1; 177 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 178 uint32_t reserved_26a : 21, 179 qos_sn_2_frag_num_state : 4, 180 qos_sn_2_more_frag_state : 1, 181 qos_sn_1_frag_num_state : 4, 182 qos_sn_1_more_frag_state : 1, 183 corrupted_due_to_fifo_delay : 1; 184 uint32_t rx_ppdu_end_marker : 32; 185 #endif 186 }; 187 188 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 189 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 190 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 191 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff 192 193 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 194 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 195 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 196 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 197 198 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 199 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 200 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 201 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff 202 203 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 204 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 205 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 206 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 207 208 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 209 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 210 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 211 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 212 213 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 214 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 215 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 216 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 217 218 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 219 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 220 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 221 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 222 223 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 224 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 225 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 226 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 227 228 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 229 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 230 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 231 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 232 233 #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 234 #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 235 #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 236 #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 237 238 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 239 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 240 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 241 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 242 243 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 244 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 245 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 246 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 247 248 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 249 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 250 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 251 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 252 253 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 254 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 255 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 256 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 257 258 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 259 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 260 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 261 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 262 263 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 264 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 265 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 266 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 267 268 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 269 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 270 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 271 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 272 273 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 274 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 275 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 276 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 277 278 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 279 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 280 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 281 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 282 283 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 284 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 285 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 286 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 287 288 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 289 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 290 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 291 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 292 293 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 294 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 295 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 296 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 297 298 #define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 299 #define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 300 #define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 301 #define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 302 303 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 304 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 305 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 306 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff 307 308 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 309 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 310 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 311 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 312 313 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 314 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 315 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 316 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 317 318 #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 319 #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 320 #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 321 #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 322 323 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 324 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 325 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 326 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 327 328 #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 329 #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 330 #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 331 #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 332 333 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 334 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 335 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 336 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff 337 338 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 339 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 340 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 341 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 342 343 #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 344 #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 345 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 346 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff 347 348 #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 349 #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 350 #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 351 #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 352 353 #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 354 #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 355 #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 356 #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 357 358 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 359 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 360 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 361 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 362 363 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 364 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 365 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 366 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 367 368 #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 369 #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 370 #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 371 #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 372 373 #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 374 #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 375 #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 376 #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff 377 378 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 379 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 380 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 381 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 382 383 #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 384 #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 385 #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 386 #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 387 388 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 389 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 390 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 391 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 392 393 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 394 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 395 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 396 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 397 398 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 399 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 400 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 401 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 402 403 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 404 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 405 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 406 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 407 408 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 409 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 410 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 411 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 412 413 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 414 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 415 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 416 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 417 418 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 419 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 420 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 421 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff 422 423 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 424 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 425 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 426 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 427 428 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 429 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 430 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 431 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 432 433 #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 434 #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 435 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 436 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 437 438 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 439 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 440 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 441 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 442 443 #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 444 #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 445 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 446 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 447 448 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 449 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 450 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 451 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 452 453 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 454 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 455 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 456 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 457 458 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 459 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 460 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 461 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 462 463 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 464 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 465 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 466 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 467 468 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 469 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 470 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 471 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 472 473 #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 474 #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 475 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 476 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 477 478 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 479 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 480 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 481 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c 482 483 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 484 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 485 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 486 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 487 488 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 489 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 490 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 491 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 492 493 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 494 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 495 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 496 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 497 498 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 499 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 500 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 501 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 502 503 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 504 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 505 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 506 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 507 508 #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 509 #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 510 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 511 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 512 513 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 514 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 515 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 516 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 517 518 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 519 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 520 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 521 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 522 523 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 524 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 525 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 526 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 527 528 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 529 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 530 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 531 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 532 533 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 534 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 535 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 536 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 537 538 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 539 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 540 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 541 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 542 543 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 544 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 545 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 546 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc 547 548 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 549 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 550 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 551 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 552 553 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 554 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 555 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 556 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 557 558 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 559 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 560 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 561 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 562 563 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 564 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 565 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 566 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 567 568 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 569 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 570 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 571 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 572 573 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 574 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 575 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 576 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 577 578 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 579 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 580 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 581 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 582 583 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 584 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 585 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 586 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 587 588 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 589 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 590 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 591 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 592 593 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 594 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 595 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 596 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 597 598 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 599 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 600 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 601 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f 602 603 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 604 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 605 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 606 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 607 608 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 609 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 610 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 611 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 612 613 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 614 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 615 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 616 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 617 618 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 619 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 620 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 621 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 622 623 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 624 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 625 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 626 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 627 628 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 629 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 630 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 631 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 632 633 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 634 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 635 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 636 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 637 638 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 639 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 640 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 641 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 642 643 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 644 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 645 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 646 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 647 648 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 649 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 650 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 651 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f 652 653 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 654 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 655 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 656 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 657 658 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 659 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 660 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 661 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 662 663 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 664 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 665 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 666 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 667 668 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 669 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 670 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 671 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 672 673 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 674 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 675 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 676 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 677 678 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 679 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 680 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 681 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 682 683 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 684 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 685 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 686 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 687 688 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 689 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 690 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 691 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 692 693 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 694 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 695 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 696 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 697 698 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 699 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 700 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 701 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 702 703 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 704 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 705 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 706 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 707 708 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 709 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 710 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 711 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff 712 713 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 714 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 715 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 716 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 717 718 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 719 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 720 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 721 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 722 723 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 724 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 725 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 726 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 727 728 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 729 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 730 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 731 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 732 733 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 734 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 735 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 736 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 737 738 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 739 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 740 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 741 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 742 743 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 744 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 745 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 746 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff 747 748 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 749 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 750 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 751 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 752 753 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 754 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 755 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 756 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 757 758 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 759 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 760 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 761 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 762 763 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 764 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 765 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 766 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c 767 768 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 769 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 770 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 771 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 772 773 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 774 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 775 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 776 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 777 778 #define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 779 #define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 780 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 781 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 782 783 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 784 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 785 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 786 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 787 788 #endif 789