1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ 23 #define _RXPCU_PPDU_END_LAYOUT_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 28 29 struct rxpcu_ppdu_end_layout_info { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rssi_legacy_offset : 2, 32 l_sig_a_offset : 6, 33 l_sig_b_offset : 6, 34 ht_sig_offset : 6, 35 vht_sig_a_offset : 6, 36 repeat_l_sig_a_offset : 6; 37 uint32_t he_sig_a_su_offset : 6, 38 he_sig_a_mu_dl_offset : 6, 39 he_sig_a_mu_ul_offset : 6, 40 generic_u_sig_offset : 6, 41 rssi_ht_offset : 7, 42 reserved_1a : 1; 43 uint32_t vht_sig_b_su20_offset : 7, 44 vht_sig_b_su40_offset : 7, 45 vht_sig_b_su80_offset : 7, 46 vht_sig_b_su160_offset : 7, 47 reserved_2a : 4; 48 uint32_t vht_sig_b_mu20_offset : 7, 49 vht_sig_b_mu40_offset : 7, 50 vht_sig_b_mu80_offset : 7, 51 vht_sig_b_mu160_offset : 7, 52 reserved_3a : 4; 53 uint32_t he_sig_b1_mu_offset : 7, 54 he_sig_b2_mu_offset : 7, 55 he_sig_b2_ofdma_offset : 7, 56 first_generic_eht_sig_offset : 7, 57 multiple_generic_eht_sig_included : 1, 58 reserved_4a : 3; 59 uint32_t common_user_info_offset : 7, 60 first_debug_info_offset : 8, 61 multiple_debug_info_included : 1, 62 first_other_receive_info_offset : 8, 63 multiple_other_receive_info_included : 1, 64 reserved_5a : 7; 65 uint32_t data_done_offset : 8, 66 generated_cbf_details_offset : 8, 67 pkt_end_part1_offset : 8, 68 location_offset : 8; 69 uint32_t __reserved_g_0011 : 8, 70 pkt_end_offset : 8, 71 abort_request_ack_offset : 8, 72 reserved_7a : 8; 73 uint32_t reserved_8a : 32; 74 uint32_t reserved_9a : 32; 75 #else 76 uint32_t repeat_l_sig_a_offset : 6, 77 vht_sig_a_offset : 6, 78 ht_sig_offset : 6, 79 l_sig_b_offset : 6, 80 l_sig_a_offset : 6, 81 rssi_legacy_offset : 2; 82 uint32_t reserved_1a : 1, 83 rssi_ht_offset : 7, 84 generic_u_sig_offset : 6, 85 he_sig_a_mu_ul_offset : 6, 86 he_sig_a_mu_dl_offset : 6, 87 he_sig_a_su_offset : 6; 88 uint32_t reserved_2a : 4, 89 vht_sig_b_su160_offset : 7, 90 vht_sig_b_su80_offset : 7, 91 vht_sig_b_su40_offset : 7, 92 vht_sig_b_su20_offset : 7; 93 uint32_t reserved_3a : 4, 94 vht_sig_b_mu160_offset : 7, 95 vht_sig_b_mu80_offset : 7, 96 vht_sig_b_mu40_offset : 7, 97 vht_sig_b_mu20_offset : 7; 98 uint32_t reserved_4a : 3, 99 multiple_generic_eht_sig_included : 1, 100 first_generic_eht_sig_offset : 7, 101 he_sig_b2_ofdma_offset : 7, 102 he_sig_b2_mu_offset : 7, 103 he_sig_b1_mu_offset : 7; 104 uint32_t reserved_5a : 7, 105 multiple_other_receive_info_included : 1, 106 first_other_receive_info_offset : 8, 107 multiple_debug_info_included : 1, 108 first_debug_info_offset : 8, 109 common_user_info_offset : 7; 110 uint32_t location_offset : 8, 111 pkt_end_part1_offset : 8, 112 generated_cbf_details_offset : 8, 113 data_done_offset : 8; 114 uint32_t reserved_7a : 8, 115 abort_request_ack_offset : 8, 116 pkt_end_offset : 8, 117 __reserved_g_0011 : 8; 118 uint32_t reserved_8a : 32; 119 uint32_t reserved_9a : 32; 120 #endif 121 }; 122 123 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 124 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 125 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 126 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 127 128 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 129 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 130 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 131 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc 132 133 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 134 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 135 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 136 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 137 138 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 139 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 140 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 141 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 142 143 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 144 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 145 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 146 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 147 148 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 149 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 150 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 151 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 152 153 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 154 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 155 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 156 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f 157 158 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 159 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 160 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 161 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 162 163 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 164 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 165 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 166 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 167 168 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 169 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 170 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 171 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 172 173 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 174 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 175 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 176 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 177 178 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 179 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 180 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 181 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 182 183 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 184 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 185 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 186 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f 187 188 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 189 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 190 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 191 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 192 193 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 194 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 195 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 196 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 197 198 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 199 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 200 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 201 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 202 203 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 204 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 205 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 206 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 207 208 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c 209 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 210 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 211 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f 212 213 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c 214 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 215 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 216 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 217 218 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c 219 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 220 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 221 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 222 223 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c 224 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 225 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 226 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 227 228 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c 229 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 230 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 231 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 232 233 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 234 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 235 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 236 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f 237 238 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 239 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 240 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 241 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 242 243 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 244 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 245 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 246 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 247 248 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 249 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 250 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 251 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 252 253 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 254 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 255 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 256 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 257 258 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 259 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 260 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 261 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 262 263 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 264 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 265 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 266 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f 267 268 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 269 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 270 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 271 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 272 273 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 274 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 275 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 276 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 277 278 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 279 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 280 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 281 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 282 283 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 284 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 285 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 286 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 287 288 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 289 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 290 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 291 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 292 293 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 294 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 295 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 296 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff 297 298 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 299 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 300 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 301 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 302 303 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 304 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 305 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 306 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 307 308 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 309 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 310 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 311 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 312 313 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c 314 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 315 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 316 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 317 318 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c 319 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 320 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 321 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 322 323 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c 324 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 325 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 326 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 327 328 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 329 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 330 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 331 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff 332 333 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 334 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 335 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 336 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff 337 338 #endif 339