1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _TCL_STATUS_RING_H_ 23 #define _TCL_STATUS_RING_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 28 29 struct tcl_status_ring { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t gse_ctrl : 4, 32 ase_fse_sel : 1, 33 cache_op_res : 2, 34 index_search_en : 1, 35 msdu_cnt_n : 24; 36 uint32_t msdu_byte_cnt_n : 32; 37 uint32_t msdu_timestmp_n : 32; 38 uint32_t cmd_meta_data_31_0 : 32; 39 uint32_t cmd_meta_data_63_32 : 32; 40 uint32_t hash_indx_val : 20, 41 cache_set_num : 4, 42 reserved_5a : 8; 43 uint32_t reserved_6a : 32; 44 uint32_t reserved_7a : 20, 45 ring_id : 8, 46 looping_count : 4; 47 #else 48 uint32_t msdu_cnt_n : 24, 49 index_search_en : 1, 50 cache_op_res : 2, 51 ase_fse_sel : 1, 52 gse_ctrl : 4; 53 uint32_t msdu_byte_cnt_n : 32; 54 uint32_t msdu_timestmp_n : 32; 55 uint32_t cmd_meta_data_31_0 : 32; 56 uint32_t cmd_meta_data_63_32 : 32; 57 uint32_t reserved_5a : 8, 58 cache_set_num : 4, 59 hash_indx_val : 20; 60 uint32_t reserved_6a : 32; 61 uint32_t looping_count : 4, 62 ring_id : 8, 63 reserved_7a : 20; 64 #endif 65 }; 66 67 #define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 68 #define TCL_STATUS_RING_GSE_CTRL_LSB 0 69 #define TCL_STATUS_RING_GSE_CTRL_MSB 3 70 #define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f 71 72 #define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 73 #define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 74 #define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 75 #define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 76 77 #define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 78 #define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 79 #define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 80 #define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 81 82 #define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 83 #define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 84 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 85 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 86 87 #define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 88 #define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 89 #define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 90 #define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 91 92 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 93 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 94 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 95 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff 96 97 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 98 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 99 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 100 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff 101 102 #define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c 103 #define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 104 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 105 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff 106 107 #define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 108 #define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 109 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 110 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff 111 112 #define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 113 #define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 114 #define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 115 #define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff 116 117 #define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 118 #define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 119 #define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 120 #define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 121 122 #define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 123 #define TCL_STATUS_RING_RESERVED_5A_LSB 24 124 #define TCL_STATUS_RING_RESERVED_5A_MSB 31 125 #define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 126 127 #define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 128 #define TCL_STATUS_RING_RESERVED_6A_LSB 0 129 #define TCL_STATUS_RING_RESERVED_6A_MSB 31 130 #define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff 131 132 #define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c 133 #define TCL_STATUS_RING_RESERVED_7A_LSB 0 134 #define TCL_STATUS_RING_RESERVED_7A_MSB 19 135 #define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff 136 137 #define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c 138 #define TCL_STATUS_RING_RING_ID_LSB 20 139 #define TCL_STATUS_RING_RING_ID_MSB 27 140 #define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 141 142 #define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c 143 #define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 144 #define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 145 #define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 146 147 #endif 148