1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_FES_STATUS_1K_BA_H_ 21 #define _TX_FES_STATUS_1K_BA_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 26 27 #define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 28 29 struct tx_fes_status_1k_ba { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t ack_ba_status_type : 1, 32 ba_type : 1, 33 ba_tid : 4, 34 unexpected_ack_or_ba : 1, 35 response_timeout : 1, 36 ack_frame_rssi : 8, 37 ssn : 12, 38 reserved_0b : 4; 39 uint32_t sw_peer_id : 16, 40 reserved_1a : 16; 41 uint32_t ba_bitmap_31_0 : 32; 42 uint32_t ba_bitmap_63_32 : 32; 43 uint32_t ba_bitmap_95_64 : 32; 44 uint32_t ba_bitmap_127_96 : 32; 45 uint32_t ba_bitmap_159_128 : 32; 46 uint32_t ba_bitmap_191_160 : 32; 47 uint32_t ba_bitmap_223_192 : 32; 48 uint32_t ba_bitmap_255_224 : 32; 49 uint32_t ba_bitmap_287_256 : 32; 50 uint32_t ba_bitmap_319_288 : 32; 51 uint32_t ba_bitmap_351_320 : 32; 52 uint32_t ba_bitmap_383_352 : 32; 53 uint32_t ba_bitmap_415_384 : 32; 54 uint32_t ba_bitmap_447_416 : 32; 55 uint32_t ba_bitmap_479_448 : 32; 56 uint32_t ba_bitmap_511_480 : 32; 57 uint32_t ba_bitmap_543_512 : 32; 58 uint32_t ba_bitmap_575_544 : 32; 59 uint32_t ba_bitmap_607_576 : 32; 60 uint32_t ba_bitmap_639_608 : 32; 61 uint32_t ba_bitmap_671_640 : 32; 62 uint32_t ba_bitmap_703_672 : 32; 63 uint32_t ba_bitmap_735_704 : 32; 64 uint32_t ba_bitmap_767_736 : 32; 65 uint32_t ba_bitmap_799_768 : 32; 66 uint32_t ba_bitmap_831_800 : 32; 67 uint32_t ba_bitmap_863_832 : 32; 68 uint32_t ba_bitmap_895_864 : 32; 69 uint32_t ba_bitmap_927_896 : 32; 70 uint32_t ba_bitmap_959_928 : 32; 71 uint32_t ba_bitmap_991_960 : 32; 72 uint32_t ba_bitmap_1023_992 : 32; 73 #else 74 uint32_t reserved_0b : 4, 75 ssn : 12, 76 ack_frame_rssi : 8, 77 response_timeout : 1, 78 unexpected_ack_or_ba : 1, 79 ba_tid : 4, 80 ba_type : 1, 81 ack_ba_status_type : 1; 82 uint32_t reserved_1a : 16, 83 sw_peer_id : 16; 84 uint32_t ba_bitmap_31_0 : 32; 85 uint32_t ba_bitmap_63_32 : 32; 86 uint32_t ba_bitmap_95_64 : 32; 87 uint32_t ba_bitmap_127_96 : 32; 88 uint32_t ba_bitmap_159_128 : 32; 89 uint32_t ba_bitmap_191_160 : 32; 90 uint32_t ba_bitmap_223_192 : 32; 91 uint32_t ba_bitmap_255_224 : 32; 92 uint32_t ba_bitmap_287_256 : 32; 93 uint32_t ba_bitmap_319_288 : 32; 94 uint32_t ba_bitmap_351_320 : 32; 95 uint32_t ba_bitmap_383_352 : 32; 96 uint32_t ba_bitmap_415_384 : 32; 97 uint32_t ba_bitmap_447_416 : 32; 98 uint32_t ba_bitmap_479_448 : 32; 99 uint32_t ba_bitmap_511_480 : 32; 100 uint32_t ba_bitmap_543_512 : 32; 101 uint32_t ba_bitmap_575_544 : 32; 102 uint32_t ba_bitmap_607_576 : 32; 103 uint32_t ba_bitmap_639_608 : 32; 104 uint32_t ba_bitmap_671_640 : 32; 105 uint32_t ba_bitmap_703_672 : 32; 106 uint32_t ba_bitmap_735_704 : 32; 107 uint32_t ba_bitmap_767_736 : 32; 108 uint32_t ba_bitmap_799_768 : 32; 109 uint32_t ba_bitmap_831_800 : 32; 110 uint32_t ba_bitmap_863_832 : 32; 111 uint32_t ba_bitmap_895_864 : 32; 112 uint32_t ba_bitmap_927_896 : 32; 113 uint32_t ba_bitmap_959_928 : 32; 114 uint32_t ba_bitmap_991_960 : 32; 115 uint32_t ba_bitmap_1023_992 : 32; 116 #endif 117 }; 118 119 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 120 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 121 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 122 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 123 124 #define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 125 #define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 126 #define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 127 #define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 128 129 #define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 130 #define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 131 #define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 132 #define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c 133 134 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 135 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 136 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 137 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 138 139 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 140 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 141 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 142 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 143 144 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 145 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 146 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 147 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 148 149 #define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 150 #define TX_FES_STATUS_1K_BA_SSN_LSB 16 151 #define TX_FES_STATUS_1K_BA_SSN_MSB 27 152 #define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 153 154 #define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 155 #define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 156 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 157 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 158 159 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 160 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 161 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 162 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 163 164 #define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 165 #define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 166 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 167 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 168 169 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 170 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 171 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 172 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff 173 174 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 175 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 176 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 177 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 178 179 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 180 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 181 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 182 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff 183 184 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 185 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 186 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 187 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 188 189 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 190 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 191 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 192 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff 193 194 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 195 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 196 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 197 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 198 199 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 200 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 201 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 202 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff 203 204 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 205 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 206 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 207 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 208 209 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 210 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 211 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 212 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff 213 214 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 215 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 216 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 217 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 218 219 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 220 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 221 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 222 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff 223 224 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 225 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 226 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 227 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 228 229 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 230 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 231 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 232 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff 233 234 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 235 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 236 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 237 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 238 239 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 240 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 241 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 242 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff 243 244 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 245 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 246 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 247 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 248 249 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 250 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 251 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 252 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff 253 254 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 255 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 256 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 257 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 258 259 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 260 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 261 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 262 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff 263 264 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 265 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 266 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 267 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 268 269 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 270 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 271 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 272 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff 273 274 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 275 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 276 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 277 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 278 279 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 280 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 281 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 282 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff 283 284 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 285 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 286 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 287 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 288 289 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 290 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 291 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 292 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff 293 294 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 295 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 296 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 297 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 298 299 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 300 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 301 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 302 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff 303 304 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 305 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 306 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 307 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 308 309 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 310 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 311 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 312 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff 313 314 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 315 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 316 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 317 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 318 319 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 320 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 321 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 322 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff 323 324 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 325 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 326 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 327 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 328 329 #endif 330