1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_FES_STATUS_END_H_ 21 #define _TX_FES_STATUS_END_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "phytx_abort_request_info.h" 26 #define NUM_OF_DWORDS_TX_FES_STATUS_END 22 27 28 #define NUM_OF_QWORDS_TX_FES_STATUS_END 11 29 30 struct tx_fes_status_end { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t prot_coex_bt_tx_while_wlan_tx : 1, 33 prot_coex_bt_tx_while_wlan_rx : 1, 34 prot_coex_wan_tx_while_wlan_tx : 1, 35 prot_coex_wan_tx_while_wlan_rx : 1, 36 prot_coex_wlan_tx_while_wlan_tx : 1, 37 prot_coex_wlan_tx_while_wlan_rx : 1, 38 coex_bt_tx_while_wlan_tx : 1, 39 coex_bt_tx_while_wlan_rx : 1, 40 coex_wan_tx_while_wlan_tx : 1, 41 coex_wan_tx_while_wlan_rx : 1, 42 coex_wlan_tx_while_wlan_tx : 1, 43 coex_wlan_tx_while_wlan_rx : 1, 44 global_data_underflow_warning : 1, 45 global_fes_transmit_result : 4, 46 cbf_bw_received_valid : 1, 47 cbf_bw_received : 3, 48 actual_received_ack_type : 4, 49 sta_response_count : 6, 50 dpdtrain_done : 1; 51 struct phytx_abort_request_info phytx_abort_request_info_details; 52 uint16_t reserved_after_struct16 : 4, 53 brp_info_valid : 1, 54 reserved_1a : 6, 55 phytx_pkt_end_info_valid : 1, 56 phytx_abort_request_info_valid : 1, 57 fes_in_11ax_trigger_response_config : 1, 58 null_delim_inserted_before_mpdus : 1, 59 only_null_delim_sent : 1; 60 uint32_t start_of_frame_timestamp_15_0 : 16, 61 start_of_frame_timestamp_31_16 : 16; 62 uint32_t end_of_frame_timestamp_15_0 : 16, 63 end_of_frame_timestamp_31_16 : 16; 64 uint32_t terminate___reserved_g_0005_sequence : 1, 65 reserved_4a : 7, 66 timing_status : 2, 67 response_type : 5, 68 r2r_end_status_to_follow : 1, 69 transmit_delay : 16; 70 uint32_t tx_group_delay : 12, 71 reserved_5a : 4, 72 tpc_dbg_info_cmn_15_0 : 16; 73 uint32_t tpc_dbg_info_cmn_31_16 : 16, 74 tpc_dbg_info_47_32 : 16; 75 uint32_t tpc_dbg_info_chn1_15_0 : 16, 76 tpc_dbg_info_chn1_31_16 : 16; 77 uint32_t tpc_dbg_info_chn1_47_32 : 16, 78 tpc_dbg_info_chn1_63_48 : 16; 79 uint32_t tpc_dbg_info_chn1_79_64 : 16, 80 tpc_dbg_info_chn2_15_0 : 16; 81 uint32_t tpc_dbg_info_chn2_31_16 : 16, 82 tpc_dbg_info_chn2_47_32 : 16; 83 uint32_t tpc_dbg_info_chn2_63_48 : 16, 84 tpc_dbg_info_chn2_79_64 : 16; 85 uint32_t phytx_tx_end_sw_info_15_0 : 16, 86 phytx_tx_end_sw_info_31_16 : 16; 87 uint32_t phytx_tx_end_sw_info_47_32 : 16, 88 phytx_tx_end_sw_info_63_48 : 16; 89 uint32_t beamform_masked_user_bitmap_15_0 : 16, 90 beamform_masked_user_bitmap_31_16 : 16; 91 uint32_t cbf_segment_request_mask : 8, 92 cbf_segment_sent_mask : 8, 93 highest_achieved_data_null_ratio : 5, 94 use_alt_power_sr : 1, 95 static_2_pwr_mode_status : 1, 96 obss_srg_opport_transmit_status : 1, 97 srp_based_transmit_status : 1, 98 obss_pd_based_transmit_status : 1, 99 beamform_masked_user_bitmap_36_32 : 5, 100 pdg_mpdu_ready : 1; 101 uint32_t pdg_mpdu_count : 16, 102 pdg_est_mpdu_tx_count : 16; 103 uint32_t pdg_overview_length : 24, 104 txop_duration : 7, 105 pdg_dropped_mpdu_warning : 1; 106 uint32_t packet_extension_a_factor : 2, 107 packet_extension_pe_disambiguity : 1, 108 packet_extension : 3, 109 fec_type : 1, 110 stbc : 1, 111 num_data_symbols : 16, 112 ru_size : 4, 113 reserved_17a : 4; 114 uint32_t num_ltf_symbols : 3, 115 ltf_size : 2, 116 cp_setting : 2, 117 reserved_18a : 5, 118 dcm : 1, 119 ldpc_extra_symbol : 1, 120 force_extra_symbol : 1, 121 reserved_18b : 1, 122 tx_pwr_shared : 8, 123 tx_pwr_unshared : 8; 124 uint32_t __reserved_g_0005_active_user_map : 16, 125 __reserved_g_0005_sent_dummy_tx : 1, 126 __reserved_g_0005_ftm_frame_sent : 1, 127 reserved_20a : 6, 128 cv_corr_status : 8; 129 uint32_t current_tx_duration : 16, 130 reserved_21a : 16; 131 #else 132 uint32_t dpdtrain_done : 1, 133 sta_response_count : 6, 134 actual_received_ack_type : 4, 135 cbf_bw_received : 3, 136 cbf_bw_received_valid : 1, 137 global_fes_transmit_result : 4, 138 global_data_underflow_warning : 1, 139 coex_wlan_tx_while_wlan_rx : 1, 140 coex_wlan_tx_while_wlan_tx : 1, 141 coex_wan_tx_while_wlan_rx : 1, 142 coex_wan_tx_while_wlan_tx : 1, 143 coex_bt_tx_while_wlan_rx : 1, 144 coex_bt_tx_while_wlan_tx : 1, 145 prot_coex_wlan_tx_while_wlan_rx : 1, 146 prot_coex_wlan_tx_while_wlan_tx : 1, 147 prot_coex_wan_tx_while_wlan_rx : 1, 148 prot_coex_wan_tx_while_wlan_tx : 1, 149 prot_coex_bt_tx_while_wlan_rx : 1, 150 prot_coex_bt_tx_while_wlan_tx : 1; 151 uint32_t only_null_delim_sent : 1, 152 null_delim_inserted_before_mpdus : 1, 153 fes_in_11ax_trigger_response_config : 1, 154 phytx_abort_request_info_valid : 1, 155 phytx_pkt_end_info_valid : 1, 156 reserved_1a : 6, 157 brp_info_valid : 1, 158 reserved_after_struct16 : 4; 159 struct phytx_abort_request_info phytx_abort_request_info_details; 160 uint32_t start_of_frame_timestamp_31_16 : 16, 161 start_of_frame_timestamp_15_0 : 16; 162 uint32_t end_of_frame_timestamp_31_16 : 16, 163 end_of_frame_timestamp_15_0 : 16; 164 uint32_t transmit_delay : 16, 165 r2r_end_status_to_follow : 1, 166 response_type : 5, 167 timing_status : 2, 168 reserved_4a : 7, 169 terminate___reserved_g_0005_sequence : 1; 170 uint32_t tpc_dbg_info_cmn_15_0 : 16, 171 reserved_5a : 4, 172 tx_group_delay : 12; 173 uint32_t tpc_dbg_info_47_32 : 16, 174 tpc_dbg_info_cmn_31_16 : 16; 175 uint32_t tpc_dbg_info_chn1_31_16 : 16, 176 tpc_dbg_info_chn1_15_0 : 16; 177 uint32_t tpc_dbg_info_chn1_63_48 : 16, 178 tpc_dbg_info_chn1_47_32 : 16; 179 uint32_t tpc_dbg_info_chn2_15_0 : 16, 180 tpc_dbg_info_chn1_79_64 : 16; 181 uint32_t tpc_dbg_info_chn2_47_32 : 16, 182 tpc_dbg_info_chn2_31_16 : 16; 183 uint32_t tpc_dbg_info_chn2_79_64 : 16, 184 tpc_dbg_info_chn2_63_48 : 16; 185 uint32_t phytx_tx_end_sw_info_31_16 : 16, 186 phytx_tx_end_sw_info_15_0 : 16; 187 uint32_t phytx_tx_end_sw_info_63_48 : 16, 188 phytx_tx_end_sw_info_47_32 : 16; 189 uint32_t beamform_masked_user_bitmap_31_16 : 16, 190 beamform_masked_user_bitmap_15_0 : 16; 191 uint32_t pdg_mpdu_ready : 1, 192 beamform_masked_user_bitmap_36_32 : 5, 193 obss_pd_based_transmit_status : 1, 194 srp_based_transmit_status : 1, 195 obss_srg_opport_transmit_status : 1, 196 static_2_pwr_mode_status : 1, 197 use_alt_power_sr : 1, 198 highest_achieved_data_null_ratio : 5, 199 cbf_segment_sent_mask : 8, 200 cbf_segment_request_mask : 8; 201 uint32_t pdg_est_mpdu_tx_count : 16, 202 pdg_mpdu_count : 16; 203 uint32_t pdg_dropped_mpdu_warning : 1, 204 txop_duration : 7, 205 pdg_overview_length : 24; 206 uint32_t reserved_17a : 4, 207 ru_size : 4, 208 num_data_symbols : 16, 209 stbc : 1, 210 fec_type : 1, 211 packet_extension : 3, 212 packet_extension_pe_disambiguity : 1, 213 packet_extension_a_factor : 2; 214 uint32_t tx_pwr_unshared : 8, 215 tx_pwr_shared : 8, 216 reserved_18b : 1, 217 force_extra_symbol : 1, 218 ldpc_extra_symbol : 1, 219 dcm : 1, 220 reserved_18a : 5, 221 cp_setting : 2, 222 ltf_size : 2, 223 num_ltf_symbols : 3; 224 uint32_t cv_corr_status : 8, 225 reserved_20a : 6, 226 __reserved_g_0005_ftm_frame_sent : 1, 227 __reserved_g_0005_sent_dummy_tx : 1, 228 __reserved_g_0005_active_user_map : 16; 229 uint32_t reserved_21a : 16, 230 current_tx_duration : 16; 231 #endif 232 }; 233 234 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 235 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 236 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 237 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 238 239 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 240 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 241 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 242 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 243 244 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 245 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 246 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 247 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 248 249 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 250 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 251 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 252 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 253 254 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 255 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 256 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 257 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 258 259 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 260 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 261 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 262 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 263 264 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 265 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 266 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 267 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 268 269 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 270 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 271 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 272 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 273 274 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 275 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 276 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 277 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 278 279 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 280 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 281 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 282 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 283 284 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 285 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 286 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 287 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 288 289 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 290 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 291 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 292 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 293 294 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 295 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 296 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 297 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 298 299 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 300 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 301 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 302 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 303 304 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 305 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 306 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 307 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 308 309 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 310 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 311 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 312 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 313 314 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 315 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 316 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 317 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 318 319 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 320 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 321 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 322 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 323 324 #define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 325 #define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 326 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 327 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 328 329 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 330 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 331 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 332 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 333 334 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 335 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 336 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 337 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 338 339 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 340 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 341 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 342 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 343 344 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 345 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 346 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 347 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 348 349 #define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 350 #define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 351 #define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 352 #define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 353 354 #define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 355 #define TX_FES_STATUS_END_RESERVED_1A_LSB 53 356 #define TX_FES_STATUS_END_RESERVED_1A_MSB 58 357 #define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 358 359 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 360 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 361 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 362 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 363 364 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 365 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 366 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 367 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 368 369 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 370 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 371 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 372 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 373 374 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 375 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 376 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 377 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 378 379 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 380 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 381 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 382 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 383 384 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 385 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 386 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 387 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 388 389 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 390 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 391 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 392 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 393 394 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 395 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 396 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 397 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 398 399 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 400 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 401 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 402 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 403 404 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 405 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 406 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 407 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 408 409 #define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 410 #define TX_FES_STATUS_END_RESERVED_4A_LSB 1 411 #define TX_FES_STATUS_END_RESERVED_4A_MSB 7 412 #define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe 413 414 #define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 415 #define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 416 #define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 417 #define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 418 419 #define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 420 #define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 421 #define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 422 #define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 423 424 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 425 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 426 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 427 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 428 429 #define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 430 #define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 431 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 432 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 433 434 #define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 435 #define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 436 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 437 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 438 439 #define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 440 #define TX_FES_STATUS_END_RESERVED_5A_LSB 44 441 #define TX_FES_STATUS_END_RESERVED_5A_MSB 47 442 #define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 443 444 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 445 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 446 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 447 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 448 449 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 450 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 451 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 452 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff 453 454 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 455 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 456 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 457 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 458 459 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 460 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 461 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 462 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 463 464 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 465 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 466 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 467 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 468 469 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 470 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 471 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 472 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 473 474 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 475 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 476 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 477 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 478 479 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 480 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 481 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 482 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 483 484 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 485 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 486 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 487 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 488 489 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 490 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 491 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 492 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 493 494 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 495 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 496 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 497 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 498 499 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 500 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 501 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 502 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 503 504 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 505 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 506 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 507 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 508 509 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 510 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 511 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 512 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 513 514 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 515 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 516 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 517 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 518 519 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 520 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 521 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 522 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 523 524 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 525 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 526 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 527 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 528 529 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 530 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 531 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 532 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff 533 534 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 535 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 536 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 537 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 538 539 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 540 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 541 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 542 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 543 544 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 545 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 546 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 547 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 548 549 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 550 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 551 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 552 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 553 554 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 555 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 556 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 557 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 558 559 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 560 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 561 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 562 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 563 564 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 565 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 566 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 567 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 568 569 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 570 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 571 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 572 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 573 574 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 575 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 576 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 577 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 578 579 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 580 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 581 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 582 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 583 584 #define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 585 #define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 586 #define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 587 #define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 588 589 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 590 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 591 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 592 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff 593 594 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 595 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 596 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 597 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 598 599 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 600 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 601 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 602 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 603 604 #define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 605 #define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 606 #define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 607 #define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 608 609 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 610 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 611 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 612 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 613 614 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 615 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 616 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 617 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 618 619 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 620 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 621 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 622 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 623 624 #define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 625 #define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 626 #define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 627 #define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 628 629 #define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 630 #define TX_FES_STATUS_END_FEC_TYPE_LSB 6 631 #define TX_FES_STATUS_END_FEC_TYPE_MSB 6 632 #define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 633 634 #define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 635 #define TX_FES_STATUS_END_STBC_LSB 7 636 #define TX_FES_STATUS_END_STBC_MSB 7 637 #define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 638 639 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 640 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 641 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 642 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 643 644 #define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 645 #define TX_FES_STATUS_END_RU_SIZE_LSB 24 646 #define TX_FES_STATUS_END_RU_SIZE_MSB 27 647 #define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 648 649 #define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 650 #define TX_FES_STATUS_END_RESERVED_17A_LSB 28 651 #define TX_FES_STATUS_END_RESERVED_17A_MSB 31 652 #define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 653 654 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 655 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 656 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 657 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 658 659 #define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 660 #define TX_FES_STATUS_END_LTF_SIZE_LSB 35 661 #define TX_FES_STATUS_END_LTF_SIZE_MSB 36 662 #define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 663 664 #define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 665 #define TX_FES_STATUS_END_CP_SETTING_LSB 37 666 #define TX_FES_STATUS_END_CP_SETTING_MSB 38 667 #define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 668 669 #define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 670 #define TX_FES_STATUS_END_RESERVED_18A_LSB 39 671 #define TX_FES_STATUS_END_RESERVED_18A_MSB 43 672 #define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 673 674 #define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 675 #define TX_FES_STATUS_END_DCM_LSB 44 676 #define TX_FES_STATUS_END_DCM_MSB 44 677 #define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 678 679 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 680 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 681 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 682 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 683 684 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 685 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 686 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 687 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 688 689 #define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 690 #define TX_FES_STATUS_END_RESERVED_18B_LSB 47 691 #define TX_FES_STATUS_END_RESERVED_18B_MSB 47 692 #define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 693 694 #define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 695 #define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 696 #define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 697 #define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 698 699 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 700 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 701 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 702 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 703 704 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 705 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 706 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 707 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff 708 709 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 710 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 711 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 712 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 713 714 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 715 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 716 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 717 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 718 719 #define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 720 #define TX_FES_STATUS_END_RESERVED_20A_LSB 18 721 #define TX_FES_STATUS_END_RESERVED_20A_MSB 23 722 #define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 723 724 #define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 725 #define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 726 #define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 727 #define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 728 729 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 730 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 731 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 732 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 733 734 #define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 735 #define TX_FES_STATUS_END_RESERVED_21A_LSB 48 736 #define TX_FES_STATUS_END_RESERVED_21A_MSB 63 737 #define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 738 739 #endif 740