1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_FES_STATUS_USER_PPDU_H_ 21 #define _TX_FES_STATUS_USER_PPDU_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 26 27 #define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 28 29 struct tx_fes_status_user_ppdu { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t underflow_mpdu_count : 9, 32 data_underflow_warning : 2, 33 bw_drop_underflow_warning : 1, 34 qc_eosp_setting : 1, 35 fc_more_data_setting : 1, 36 fc_pwr_mgt_setting : 1, 37 mpdu_tx_count : 9, 38 user_blocked : 1, 39 pre_trig_response_delim_count : 7; 40 uint32_t underflow_byte_count : 16, 41 coex_abort_mpdu_count_valid : 1, 42 coex_abort_mpdu_count : 9, 43 transmitted_tid : 4, 44 txdma_dropped_mpdu_warning : 1, 45 reserved_1 : 1; 46 uint32_t duration : 16, 47 num_eof_delim_added : 16; 48 uint32_t psdu_octet : 24, 49 qos_buf_state : 8; 50 uint32_t num_null_delim_added : 22, 51 reserved_4a : 2, 52 cv_corr_user_valid_in_phy : 1, 53 nss : 3, 54 mcs : 4; 55 uint32_t ht_control : 32; 56 #else 57 uint32_t pre_trig_response_delim_count : 7, 58 user_blocked : 1, 59 mpdu_tx_count : 9, 60 fc_pwr_mgt_setting : 1, 61 fc_more_data_setting : 1, 62 qc_eosp_setting : 1, 63 bw_drop_underflow_warning : 1, 64 data_underflow_warning : 2, 65 underflow_mpdu_count : 9; 66 uint32_t reserved_1 : 1, 67 txdma_dropped_mpdu_warning : 1, 68 transmitted_tid : 4, 69 coex_abort_mpdu_count : 9, 70 coex_abort_mpdu_count_valid : 1, 71 underflow_byte_count : 16; 72 uint32_t num_eof_delim_added : 16, 73 duration : 16; 74 uint32_t qos_buf_state : 8, 75 psdu_octet : 24; 76 uint32_t mcs : 4, 77 nss : 3, 78 cv_corr_user_valid_in_phy : 1, 79 reserved_4a : 2, 80 num_null_delim_added : 22; 81 uint32_t ht_control : 32; 82 #endif 83 }; 84 85 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 86 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 87 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 88 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 89 90 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 91 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 92 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 93 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 94 95 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 96 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 97 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 98 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 99 100 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 101 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 102 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 103 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 104 105 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 106 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 107 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 108 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 109 110 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 111 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 112 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 113 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 114 115 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 116 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 117 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 118 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 119 120 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 121 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 122 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 123 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 124 125 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 126 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 127 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 128 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 129 130 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 131 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 132 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 133 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 134 135 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 136 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 137 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 138 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 139 140 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 141 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 142 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 143 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 144 145 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 146 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 147 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 148 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 149 150 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 151 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 152 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 153 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 154 155 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 156 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 157 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 158 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 159 160 #define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 161 #define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 162 #define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 163 #define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff 164 165 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 166 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 167 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 168 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 169 170 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 171 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 172 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 173 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 174 175 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 176 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 177 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 178 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 179 180 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 181 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 182 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 183 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff 184 185 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 186 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 187 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 188 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 189 190 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 191 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 192 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 193 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 194 195 #define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 196 #define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 197 #define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 198 #define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 199 200 #define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 201 #define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 202 #define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 203 #define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 204 205 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 206 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 207 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 208 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 209 210 #endif 211