1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_MPDU_START_H_ 21 #define _TX_MPDU_START_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_TX_MPDU_START 10 26 27 #define NUM_OF_QWORDS_TX_MPDU_START 5 28 29 struct tx_mpdu_start { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t mpdu_length : 14, 32 frame_not_from_tqm : 1, 33 vht_control_present : 1, 34 mpdu_header_length : 8, 35 retry_count : 7, 36 wds : 1; 37 uint32_t pn_31_0 : 32; 38 uint32_t pn_47_32 : 16, 39 mpdu_sequence_number : 12, 40 raw_already_encrypted : 1, 41 frame_type : 2, 42 txdma_dropped_mpdu_warning : 1; 43 uint32_t iv_byte_0 : 8, 44 iv_byte_1 : 8, 45 iv_byte_2 : 8, 46 iv_byte_3 : 8; 47 uint32_t iv_byte_4 : 8, 48 iv_byte_5 : 8, 49 iv_byte_6 : 8, 50 iv_byte_7 : 8; 51 uint32_t iv_byte_8 : 8, 52 iv_byte_9 : 8, 53 iv_byte_10 : 8, 54 iv_byte_11 : 8; 55 uint32_t iv_byte_12 : 8, 56 iv_byte_13 : 8, 57 iv_byte_14 : 8, 58 iv_byte_15 : 8; 59 uint32_t iv_byte_16 : 8, 60 iv_byte_17 : 8, 61 iv_len : 5, 62 icv_len : 5, 63 vht_control_offset : 6; 64 uint32_t mpdu_type : 1, 65 transmit_bw_restriction : 1, 66 allowed_transmit_bw : 4, 67 tx_notify_frame : 3, 68 reserved_8a : 23; 69 uint32_t tlv64_padding : 32; 70 #else 71 uint32_t wds : 1, 72 retry_count : 7, 73 mpdu_header_length : 8, 74 vht_control_present : 1, 75 frame_not_from_tqm : 1, 76 mpdu_length : 14; 77 uint32_t pn_31_0 : 32; 78 uint32_t txdma_dropped_mpdu_warning : 1, 79 frame_type : 2, 80 raw_already_encrypted : 1, 81 mpdu_sequence_number : 12, 82 pn_47_32 : 16; 83 uint32_t iv_byte_3 : 8, 84 iv_byte_2 : 8, 85 iv_byte_1 : 8, 86 iv_byte_0 : 8; 87 uint32_t iv_byte_7 : 8, 88 iv_byte_6 : 8, 89 iv_byte_5 : 8, 90 iv_byte_4 : 8; 91 uint32_t iv_byte_11 : 8, 92 iv_byte_10 : 8, 93 iv_byte_9 : 8, 94 iv_byte_8 : 8; 95 uint32_t iv_byte_15 : 8, 96 iv_byte_14 : 8, 97 iv_byte_13 : 8, 98 iv_byte_12 : 8; 99 uint32_t vht_control_offset : 6, 100 icv_len : 5, 101 iv_len : 5, 102 iv_byte_17 : 8, 103 iv_byte_16 : 8; 104 uint32_t reserved_8a : 23, 105 tx_notify_frame : 3, 106 allowed_transmit_bw : 4, 107 transmit_bw_restriction : 1, 108 mpdu_type : 1; 109 uint32_t tlv64_padding : 32; 110 #endif 111 }; 112 113 #define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 114 #define TX_MPDU_START_MPDU_LENGTH_LSB 0 115 #define TX_MPDU_START_MPDU_LENGTH_MSB 13 116 #define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff 117 118 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 119 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 120 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 121 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 122 123 #define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 124 #define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 125 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 126 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 127 128 #define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 129 #define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 130 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 131 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 132 133 #define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 134 #define TX_MPDU_START_RETRY_COUNT_LSB 24 135 #define TX_MPDU_START_RETRY_COUNT_MSB 30 136 #define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 137 138 #define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 139 #define TX_MPDU_START_WDS_LSB 31 140 #define TX_MPDU_START_WDS_MSB 31 141 #define TX_MPDU_START_WDS_MASK 0x0000000080000000 142 143 #define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 144 #define TX_MPDU_START_PN_31_0_LSB 32 145 #define TX_MPDU_START_PN_31_0_MSB 63 146 #define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 147 148 #define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 149 #define TX_MPDU_START_PN_47_32_LSB 0 150 #define TX_MPDU_START_PN_47_32_MSB 15 151 #define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff 152 153 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 154 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 155 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 156 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 157 158 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 159 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 160 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 161 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 162 163 #define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 164 #define TX_MPDU_START_FRAME_TYPE_LSB 29 165 #define TX_MPDU_START_FRAME_TYPE_MSB 30 166 #define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 167 168 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 169 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 170 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 171 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 172 173 #define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 174 #define TX_MPDU_START_IV_BYTE_0_LSB 32 175 #define TX_MPDU_START_IV_BYTE_0_MSB 39 176 #define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 177 178 #define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 179 #define TX_MPDU_START_IV_BYTE_1_LSB 40 180 #define TX_MPDU_START_IV_BYTE_1_MSB 47 181 #define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 182 183 #define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 184 #define TX_MPDU_START_IV_BYTE_2_LSB 48 185 #define TX_MPDU_START_IV_BYTE_2_MSB 55 186 #define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 187 188 #define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 189 #define TX_MPDU_START_IV_BYTE_3_LSB 56 190 #define TX_MPDU_START_IV_BYTE_3_MSB 63 191 #define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 192 193 #define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 194 #define TX_MPDU_START_IV_BYTE_4_LSB 0 195 #define TX_MPDU_START_IV_BYTE_4_MSB 7 196 #define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff 197 198 #define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 199 #define TX_MPDU_START_IV_BYTE_5_LSB 8 200 #define TX_MPDU_START_IV_BYTE_5_MSB 15 201 #define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 202 203 #define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 204 #define TX_MPDU_START_IV_BYTE_6_LSB 16 205 #define TX_MPDU_START_IV_BYTE_6_MSB 23 206 #define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 207 208 #define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 209 #define TX_MPDU_START_IV_BYTE_7_LSB 24 210 #define TX_MPDU_START_IV_BYTE_7_MSB 31 211 #define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 212 213 #define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 214 #define TX_MPDU_START_IV_BYTE_8_LSB 32 215 #define TX_MPDU_START_IV_BYTE_8_MSB 39 216 #define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 217 218 #define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 219 #define TX_MPDU_START_IV_BYTE_9_LSB 40 220 #define TX_MPDU_START_IV_BYTE_9_MSB 47 221 #define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 222 223 #define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 224 #define TX_MPDU_START_IV_BYTE_10_LSB 48 225 #define TX_MPDU_START_IV_BYTE_10_MSB 55 226 #define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 227 228 #define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 229 #define TX_MPDU_START_IV_BYTE_11_LSB 56 230 #define TX_MPDU_START_IV_BYTE_11_MSB 63 231 #define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 232 233 #define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 234 #define TX_MPDU_START_IV_BYTE_12_LSB 0 235 #define TX_MPDU_START_IV_BYTE_12_MSB 7 236 #define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff 237 238 #define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 239 #define TX_MPDU_START_IV_BYTE_13_LSB 8 240 #define TX_MPDU_START_IV_BYTE_13_MSB 15 241 #define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 242 243 #define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 244 #define TX_MPDU_START_IV_BYTE_14_LSB 16 245 #define TX_MPDU_START_IV_BYTE_14_MSB 23 246 #define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 247 248 #define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 249 #define TX_MPDU_START_IV_BYTE_15_LSB 24 250 #define TX_MPDU_START_IV_BYTE_15_MSB 31 251 #define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 252 253 #define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 254 #define TX_MPDU_START_IV_BYTE_16_LSB 32 255 #define TX_MPDU_START_IV_BYTE_16_MSB 39 256 #define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 257 258 #define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 259 #define TX_MPDU_START_IV_BYTE_17_LSB 40 260 #define TX_MPDU_START_IV_BYTE_17_MSB 47 261 #define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 262 263 #define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 264 #define TX_MPDU_START_IV_LEN_LSB 48 265 #define TX_MPDU_START_IV_LEN_MSB 52 266 #define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 267 268 #define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 269 #define TX_MPDU_START_ICV_LEN_LSB 53 270 #define TX_MPDU_START_ICV_LEN_MSB 57 271 #define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 272 273 #define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 274 #define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 275 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 276 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 277 278 #define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 279 #define TX_MPDU_START_MPDU_TYPE_LSB 0 280 #define TX_MPDU_START_MPDU_TYPE_MSB 0 281 #define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 282 283 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 284 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 285 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 286 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 287 288 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 289 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 290 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 291 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c 292 293 #define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 294 #define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 295 #define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 296 #define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 297 298 #define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 299 #define TX_MPDU_START_RESERVED_8A_LSB 9 300 #define TX_MPDU_START_RESERVED_8A_MSB 31 301 #define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 302 303 #define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 304 #define TX_MPDU_START_TLV64_PADDING_LSB 32 305 #define TX_MPDU_START_TLV64_PADDING_MSB 63 306 #define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 307 308 #endif 309