1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_PEER_ENTRY_H_ 21 #define _TX_PEER_ENTRY_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_TX_PEER_ENTRY 18 26 27 #define NUM_OF_QWORDS_TX_PEER_ENTRY 9 28 29 struct tx_peer_entry { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t mac_addr_a_31_0 : 32; 32 uint32_t mac_addr_a_47_32 : 16, 33 mac_addr_b_15_0 : 16; 34 uint32_t mac_addr_b_47_16 : 32; 35 uint32_t use_ad_b : 1, 36 strip_insert_vlan_inner : 1, 37 strip_insert_vlan_outer : 1, 38 vlan_llc_mode : 1, 39 key_type : 4, 40 a_msdu_wds_ad3_ad4 : 3, 41 ignore_hard_filters : 1, 42 ignore_soft_filters : 1, 43 epd_output : 1, 44 wds : 1, 45 insert_or_strip : 1, 46 sw_filter_id : 16; 47 uint32_t temporal_key_31_0 : 32; 48 uint32_t temporal_key_63_32 : 32; 49 uint32_t temporal_key_95_64 : 32; 50 uint32_t temporal_key_127_96 : 32; 51 uint32_t temporal_key_159_128 : 32; 52 uint32_t temporal_key_191_160 : 32; 53 uint32_t temporal_key_223_192 : 32; 54 uint32_t temporal_key_255_224 : 32; 55 uint32_t sta_partial_aid : 11, 56 transmit_vif : 4, 57 block_this_user : 1, 58 mesh_amsdu_mode : 2, 59 use_qos_alt_mute_mask : 1, 60 dl_ul_direction : 1, 61 reserved_12 : 12; 62 uint32_t insert_vlan_outer_tci : 16, 63 insert_vlan_inner_tci : 16; 64 uint32_t __reserved_g_0007 : 32; 65 uint32_t __reserved_g_0008 : 16, 66 __reserved_g_0009 : 16; 67 uint32_t __reserved_g_0010 : 32; 68 uint32_t multi_link_addr_crypto_enable : 1, 69 reserved_17a : 15, 70 sw_peer_id : 16; 71 #else 72 uint32_t mac_addr_a_31_0 : 32; 73 uint32_t mac_addr_b_15_0 : 16, 74 mac_addr_a_47_32 : 16; 75 uint32_t mac_addr_b_47_16 : 32; 76 uint32_t sw_filter_id : 16, 77 insert_or_strip : 1, 78 wds : 1, 79 epd_output : 1, 80 ignore_soft_filters : 1, 81 ignore_hard_filters : 1, 82 a_msdu_wds_ad3_ad4 : 3, 83 key_type : 4, 84 vlan_llc_mode : 1, 85 strip_insert_vlan_outer : 1, 86 strip_insert_vlan_inner : 1, 87 use_ad_b : 1; 88 uint32_t temporal_key_31_0 : 32; 89 uint32_t temporal_key_63_32 : 32; 90 uint32_t temporal_key_95_64 : 32; 91 uint32_t temporal_key_127_96 : 32; 92 uint32_t temporal_key_159_128 : 32; 93 uint32_t temporal_key_191_160 : 32; 94 uint32_t temporal_key_223_192 : 32; 95 uint32_t temporal_key_255_224 : 32; 96 uint32_t reserved_12 : 12, 97 dl_ul_direction : 1, 98 use_qos_alt_mute_mask : 1, 99 mesh_amsdu_mode : 2, 100 block_this_user : 1, 101 transmit_vif : 4, 102 sta_partial_aid : 11; 103 uint32_t insert_vlan_inner_tci : 16, 104 insert_vlan_outer_tci : 16; 105 uint32_t __reserved_g_0007 : 32; 106 uint32_t __reserved_g_0009 : 16, 107 __reserved_g_0008 : 16; 108 uint32_t __reserved_g_0010 : 32; 109 uint32_t sw_peer_id : 16, 110 reserved_17a : 15, 111 multi_link_addr_crypto_enable : 1; 112 #endif 113 }; 114 115 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 116 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 117 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 118 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff 119 120 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 121 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 122 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 123 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 124 125 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 126 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 127 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 128 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 129 130 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 131 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 132 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 133 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff 134 135 #define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 136 #define TX_PEER_ENTRY_USE_AD_B_LSB 32 137 #define TX_PEER_ENTRY_USE_AD_B_MSB 32 138 #define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 139 140 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 141 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 142 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 143 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 144 145 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 146 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 147 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 148 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 149 150 #define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 151 #define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 152 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 153 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 154 155 #define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 156 #define TX_PEER_ENTRY_KEY_TYPE_LSB 36 157 #define TX_PEER_ENTRY_KEY_TYPE_MSB 39 158 #define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 159 160 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 161 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 162 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 163 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 164 165 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 166 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 167 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 168 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 169 170 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 171 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 172 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 173 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 174 175 #define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 176 #define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 177 #define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 178 #define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 179 180 #define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 181 #define TX_PEER_ENTRY_WDS_LSB 46 182 #define TX_PEER_ENTRY_WDS_MSB 46 183 #define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 184 185 #define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 186 #define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 187 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 188 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 189 190 #define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 191 #define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 192 #define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 193 #define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 194 195 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 196 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 197 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 198 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff 199 200 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 201 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 202 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 203 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 204 205 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 206 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 207 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 208 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff 209 210 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 211 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 212 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 213 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 214 215 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 216 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 217 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 218 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff 219 220 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 221 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 222 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 223 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 224 225 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 226 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 227 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 228 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff 229 230 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 231 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 232 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 233 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 234 235 #define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 236 #define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 237 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 238 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff 239 240 #define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 241 #define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 242 #define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 243 #define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 244 245 #define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 246 #define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 247 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 248 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 249 250 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 251 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 252 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 253 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 254 255 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 256 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 257 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 258 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 259 260 #define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 261 #define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 262 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 263 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 264 265 #define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 266 #define TX_PEER_ENTRY_RESERVED_12_LSB 20 267 #define TX_PEER_ENTRY_RESERVED_12_MSB 31 268 #define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 269 270 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 271 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 272 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 273 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 274 275 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 276 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 277 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 278 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 279 280 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 281 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 282 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 283 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 284 285 #define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 286 #define TX_PEER_ENTRY_RESERVED_17A_LSB 33 287 #define TX_PEER_ENTRY_RESERVED_17A_MSB 47 288 #define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 289 290 #define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 291 #define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 292 #define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 293 #define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 294 295 #endif 296