1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_QUEUE_EXTENSION_H_ 21 #define _TX_QUEUE_EXTENSION_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 26 27 #define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 28 29 struct tx_queue_extension { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t frame_ctl : 16, 32 qos_ctl : 16; 33 uint32_t ampdu_flag : 1, 34 tx_notify_no_htc_override : 1, 35 reserved_1a : 7, 36 checksum_tso_disable_for_frag : 1, 37 key_id : 8, 38 qos_buf_state_overwrite : 1, 39 buf_state_sta_id : 1, 40 buf_state_source : 1, 41 ht_control_overwrite_enable : 1, 42 ht_control_overwrite_source : 4, 43 reserved_1b : 6; 44 uint32_t ul_headroom_insertion_enable : 1, 45 ul_headroom_offset : 5, 46 bqrp_insertion_enable : 1, 47 bqrp_offset : 5, 48 ul_headroom_rsvd_7_6 : 2, 49 bqr_rsvd_9_8 : 2, 50 base_pn_63_48 : 16; 51 uint32_t base_pn_95_64 : 32; 52 uint32_t base_pn_127_96 : 32; 53 uint32_t ht_control_field_bw20 : 32; 54 uint32_t ht_control_field_bw40 : 32; 55 uint32_t ht_control_field_bw80 : 32; 56 uint32_t ht_control_field_bw160 : 32; 57 uint32_t ht_control_overwrite_mask : 32; 58 uint32_t cas_control_info : 8, 59 cas_offset : 5, 60 cas_insertion_enable : 1, 61 reserved_10a : 2, 62 ht_control_overwrite_source_for_srp : 4, 63 ht_control_overwrite_source_for_bsrp : 4, 64 reserved_10b : 6, 65 mpdu_hdr_len_override_en : 1, 66 bar_ssn_overwrite_enable : 1; 67 uint32_t bar_ssn_offset : 12, 68 mpdu_hdr_len_override_val : 9, 69 reserved_11a : 11; 70 uint32_t ht_control_field_bw320 : 32; 71 uint32_t fw2sw_info : 32; 72 #else 73 uint32_t qos_ctl : 16, 74 frame_ctl : 16; 75 uint32_t reserved_1b : 6, 76 ht_control_overwrite_source : 4, 77 ht_control_overwrite_enable : 1, 78 buf_state_source : 1, 79 buf_state_sta_id : 1, 80 qos_buf_state_overwrite : 1, 81 key_id : 8, 82 checksum_tso_disable_for_frag : 1, 83 reserved_1a : 7, 84 tx_notify_no_htc_override : 1, 85 ampdu_flag : 1; 86 uint32_t base_pn_63_48 : 16, 87 bqr_rsvd_9_8 : 2, 88 ul_headroom_rsvd_7_6 : 2, 89 bqrp_offset : 5, 90 bqrp_insertion_enable : 1, 91 ul_headroom_offset : 5, 92 ul_headroom_insertion_enable : 1; 93 uint32_t base_pn_95_64 : 32; 94 uint32_t base_pn_127_96 : 32; 95 uint32_t ht_control_field_bw20 : 32; 96 uint32_t ht_control_field_bw40 : 32; 97 uint32_t ht_control_field_bw80 : 32; 98 uint32_t ht_control_field_bw160 : 32; 99 uint32_t ht_control_overwrite_mask : 32; 100 uint32_t bar_ssn_overwrite_enable : 1, 101 mpdu_hdr_len_override_en : 1, 102 reserved_10b : 6, 103 ht_control_overwrite_source_for_bsrp : 4, 104 ht_control_overwrite_source_for_srp : 4, 105 reserved_10a : 2, 106 cas_insertion_enable : 1, 107 cas_offset : 5, 108 cas_control_info : 8; 109 uint32_t reserved_11a : 11, 110 mpdu_hdr_len_override_val : 9, 111 bar_ssn_offset : 12; 112 uint32_t ht_control_field_bw320 : 32; 113 uint32_t fw2sw_info : 32; 114 #endif 115 }; 116 117 #define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 118 #define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 119 #define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 120 #define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff 121 122 #define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 123 #define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 124 #define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 125 #define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 126 127 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 128 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 129 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 130 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 131 132 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 133 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 134 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 135 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 136 137 #define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 138 #define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 139 #define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 140 #define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 141 142 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 143 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 144 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 145 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 146 147 #define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 148 #define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 149 #define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 150 #define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 151 152 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 153 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 154 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 155 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 156 157 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 158 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 159 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 160 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 161 162 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 163 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 164 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 165 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 166 167 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 168 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 169 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 170 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 171 172 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 173 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 174 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 175 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 176 177 #define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 178 #define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 179 #define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 180 #define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 181 182 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 183 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 184 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 185 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 186 187 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 188 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 189 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 190 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e 191 192 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 193 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 194 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 195 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 196 197 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 198 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 199 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 200 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 201 202 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 203 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 204 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 205 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 206 207 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 208 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 209 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 210 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 211 212 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 213 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 214 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 215 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 216 217 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 218 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 219 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 220 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 221 222 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 223 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 224 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 225 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff 226 227 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 228 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 229 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 230 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 231 232 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 233 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 234 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 235 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff 236 237 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 238 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 239 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 240 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 241 242 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 243 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 244 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 245 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff 246 247 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 248 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 249 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 250 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 251 252 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 253 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 254 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 255 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff 256 257 #define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 258 #define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 259 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 260 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 261 262 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 263 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 264 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 265 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 266 267 #define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 268 #define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 269 #define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 270 #define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 271 272 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 273 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 274 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 275 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 276 277 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 278 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 279 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 280 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 281 282 #define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 283 #define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 284 #define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 285 #define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 286 287 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 288 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 289 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 290 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 291 292 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 293 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 294 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 295 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 296 297 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 298 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 299 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 300 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 301 302 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 303 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 304 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 305 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 306 307 #define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 308 #define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 309 #define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 310 #define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 311 312 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 313 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 314 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 315 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff 316 317 #define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 318 #define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 319 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 320 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 321 322 #endif 323