1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 21 #define _U_SIG_EHT_SU_MU_INFO_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 26 27 struct u_sig_eht_su_mu_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t phy_version : 3, 30 transmit_bw : 3, 31 dl_ul_flag : 1, 32 bss_color_id : 6, 33 txop_duration : 7, 34 disregard_0a : 5, 35 validate_0b : 1, 36 reserved_0c : 6; 37 uint32_t eht_ppdu_sig_cmn_type : 2, 38 validate_1a : 1, 39 punctured_channel_information : 5, 40 validate_1b : 1, 41 mcs_of_eht_sig : 2, 42 num_eht_sig_symbols : 5, 43 crc : 4, 44 tail : 6, 45 dot11ax_su_extended : 1, 46 reserved_1d : 3, 47 rx_ndp : 1, 48 rx_integrity_check_passed : 1; 49 #else 50 uint32_t reserved_0c : 6, 51 validate_0b : 1, 52 disregard_0a : 5, 53 txop_duration : 7, 54 bss_color_id : 6, 55 dl_ul_flag : 1, 56 transmit_bw : 3, 57 phy_version : 3; 58 uint32_t rx_integrity_check_passed : 1, 59 rx_ndp : 1, 60 reserved_1d : 3, 61 dot11ax_su_extended : 1, 62 tail : 6, 63 crc : 4, 64 num_eht_sig_symbols : 5, 65 mcs_of_eht_sig : 2, 66 validate_1b : 1, 67 punctured_channel_information : 5, 68 validate_1a : 1, 69 eht_ppdu_sig_cmn_type : 2; 70 #endif 71 }; 72 73 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 74 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 75 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 76 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 77 78 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 79 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 80 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 81 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 82 83 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 84 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 85 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 86 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 87 88 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 89 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 90 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 91 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 92 93 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 94 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 95 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 96 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 97 98 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 99 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 100 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 101 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 102 103 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 104 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 105 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 106 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 107 108 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 109 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 110 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 111 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 112 113 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 114 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 115 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 116 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 117 118 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 119 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 120 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 121 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 122 123 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 124 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 125 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 126 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 127 128 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 129 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 130 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 131 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 132 133 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 134 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 135 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 136 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 137 138 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 139 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 140 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 141 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 142 143 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 144 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 145 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 146 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 147 148 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 149 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 150 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 151 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 152 153 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 154 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 155 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 156 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 157 158 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 159 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 160 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 161 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 162 163 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 164 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 165 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 166 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 167 168 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 169 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 170 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 171 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 172 173 #endif 174