1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _U_SIG_EHT_TB_INFO_H_ 21 #define _U_SIG_EHT_TB_INFO_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 26 27 struct u_sig_eht_tb_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t phy_version : 3, 30 transmit_bw : 3, 31 dl_ul_flag : 1, 32 bss_color_id : 6, 33 txop_duration : 7, 34 disregard_0a : 6, 35 reserved_0c : 6; 36 uint32_t eht_ppdu_sig_cmn_type : 2, 37 validate_1a : 1, 38 spatial_reuse : 8, 39 disregard_1b : 5, 40 crc : 4, 41 tail : 6, 42 reserved_1c : 5, 43 rx_integrity_check_passed : 1; 44 #else 45 uint32_t reserved_0c : 6, 46 disregard_0a : 6, 47 txop_duration : 7, 48 bss_color_id : 6, 49 dl_ul_flag : 1, 50 transmit_bw : 3, 51 phy_version : 3; 52 uint32_t rx_integrity_check_passed : 1, 53 reserved_1c : 5, 54 tail : 6, 55 crc : 4, 56 disregard_1b : 5, 57 spatial_reuse : 8, 58 validate_1a : 1, 59 eht_ppdu_sig_cmn_type : 2; 60 #endif 61 }; 62 63 #define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 64 #define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 65 #define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 66 #define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 67 68 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 69 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 70 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 71 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 72 73 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 74 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 75 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 76 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 77 78 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 79 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 80 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 81 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 82 83 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 84 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 85 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 86 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 87 88 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 89 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 90 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 91 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 92 93 #define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 94 #define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 95 #define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 96 #define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 97 98 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 99 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 100 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 101 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 102 103 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 104 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 105 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 106 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 107 108 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 109 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 110 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 111 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 112 113 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 114 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 115 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 116 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 117 118 #define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 119 #define U_SIG_EHT_TB_INFO_CRC_LSB 16 120 #define U_SIG_EHT_TB_INFO_CRC_MSB 19 121 #define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 122 123 #define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 124 #define U_SIG_EHT_TB_INFO_TAIL_LSB 20 125 #define U_SIG_EHT_TB_INFO_TAIL_MSB 25 126 #define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 127 128 #define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 129 #define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 130 #define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 131 #define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 132 133 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 134 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 135 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 136 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 137 138 #endif 139