1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name #ifndef _WBM2SW_COMPLETION_RING_RX_H_ 23*5113495bSYour Name #define _WBM2SW_COMPLETION_RING_RX_H_ 24*5113495bSYour Name #if !defined(__ASSEMBLER__) 25*5113495bSYour Name #endif 26*5113495bSYour Name 27*5113495bSYour Name #include "rx_msdu_desc_info.h" 28*5113495bSYour Name #include "rx_mpdu_desc_info.h" 29*5113495bSYour Name #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 30*5113495bSYour Name 31*5113495bSYour Name struct wbm2sw_completion_ring_rx { 32*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; 34*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; 35*5113495bSYour Name uint32_t release_source_module : 3, 36*5113495bSYour Name bm_action : 3, 37*5113495bSYour Name buffer_or_desc_type : 3, 38*5113495bSYour Name return_buffer_manager : 4, 39*5113495bSYour Name reserved_2a : 2, 40*5113495bSYour Name cache_id : 1, 41*5113495bSYour Name cookie_conversion_status : 1, 42*5113495bSYour Name rxdma_push_reason : 2, 43*5113495bSYour Name rxdma_error_code : 5, 44*5113495bSYour Name reo_push_reason : 2, 45*5113495bSYour Name reo_error_code : 5, 46*5113495bSYour Name wbm_internal_error : 1; 47*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 48*5113495bSYour Name struct rx_msdu_desc_info rx_msdu_desc_info_details; 49*5113495bSYour Name uint32_t buffer_phys_addr_31_0 : 32; 50*5113495bSYour Name uint32_t buffer_phys_addr_39_32 : 8, 51*5113495bSYour Name sw_buffer_cookie : 20, 52*5113495bSYour Name looping_count : 4; 53*5113495bSYour Name #else 54*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; 55*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; 56*5113495bSYour Name uint32_t wbm_internal_error : 1, 57*5113495bSYour Name reo_error_code : 5, 58*5113495bSYour Name reo_push_reason : 2, 59*5113495bSYour Name rxdma_error_code : 5, 60*5113495bSYour Name rxdma_push_reason : 2, 61*5113495bSYour Name cookie_conversion_status : 1, 62*5113495bSYour Name cache_id : 1, 63*5113495bSYour Name reserved_2a : 2, 64*5113495bSYour Name return_buffer_manager : 4, 65*5113495bSYour Name buffer_or_desc_type : 3, 66*5113495bSYour Name bm_action : 3, 67*5113495bSYour Name release_source_module : 3; 68*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 69*5113495bSYour Name struct rx_msdu_desc_info rx_msdu_desc_info_details; 70*5113495bSYour Name uint32_t buffer_phys_addr_31_0 : 32; 71*5113495bSYour Name uint32_t looping_count : 4, 72*5113495bSYour Name sw_buffer_cookie : 20, 73*5113495bSYour Name buffer_phys_addr_39_32 : 8; 74*5113495bSYour Name #endif 75*5113495bSYour Name }; 76*5113495bSYour Name 77*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 78*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 79*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 80*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 81*5113495bSYour Name 82*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 83*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 84*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 85*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 86*5113495bSYour Name 87*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 88*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 89*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 90*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 91*5113495bSYour Name 92*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 93*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 94*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 95*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 96*5113495bSYour Name 97*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 98*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 99*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 100*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 101*5113495bSYour Name 102*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 103*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 104*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 105*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 106*5113495bSYour Name 107*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 108*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 109*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 110*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 111*5113495bSYour Name 112*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 113*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 114*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 115*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 116*5113495bSYour Name 117*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 118*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 119*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 120*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 121*5113495bSYour Name 122*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 123*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 124*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 125*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 126*5113495bSYour Name 127*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 128*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 129*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 130*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 131*5113495bSYour Name 132*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 133*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 134*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 135*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 136*5113495bSYour Name 137*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 138*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 139*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 140*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 141*5113495bSYour Name 142*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 143*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 144*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 145*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 146*5113495bSYour Name 147*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 148*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 149*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 150*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 151*5113495bSYour Name 152*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 153*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 154*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 155*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 156*5113495bSYour Name 157*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 158*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 159*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 160*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 161*5113495bSYour Name 162*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 163*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 164*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 165*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 166*5113495bSYour Name 167*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 168*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 169*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 170*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 171*5113495bSYour Name 172*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 173*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 174*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 175*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 176*5113495bSYour Name 177*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 178*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 179*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 180*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 181*5113495bSYour Name 182*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 183*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 184*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 185*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 186*5113495bSYour Name 187*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 188*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 189*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 190*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 191*5113495bSYour Name 192*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 193*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 194*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 195*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 196*5113495bSYour Name 197*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 198*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 199*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 200*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 201*5113495bSYour Name 202*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 203*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 204*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 205*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 206*5113495bSYour Name 207*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 208*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 209*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 210*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 211*5113495bSYour Name 212*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 213*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 214*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 215*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 216*5113495bSYour Name 217*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 218*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 219*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 220*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 221*5113495bSYour Name 222*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 223*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 224*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 225*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 226*5113495bSYour Name 227*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 228*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 229*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 230*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 231*5113495bSYour Name 232*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 233*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 234*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 235*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 236*5113495bSYour Name 237*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 238*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 239*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 240*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 241*5113495bSYour Name 242*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 243*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 244*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 245*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 246*5113495bSYour Name 247*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 248*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 249*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 250*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 251*5113495bSYour Name 252*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 253*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 254*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 255*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 256*5113495bSYour Name 257*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 258*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 259*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 260*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 261*5113495bSYour Name 262*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 263*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 264*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 265*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 266*5113495bSYour Name 267*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 268*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 269*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 270*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 271*5113495bSYour Name 272*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 273*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 274*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 275*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 276*5113495bSYour Name 277*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 278*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 279*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 280*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 281*5113495bSYour Name 282*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 283*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 284*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 285*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 286*5113495bSYour Name 287*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 288*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 289*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 290*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 291*5113495bSYour Name 292*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 293*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 294*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 295*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff 296*5113495bSYour Name 297*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c 298*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 299*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 300*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff 301*5113495bSYour Name 302*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c 303*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 304*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 305*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 306*5113495bSYour Name 307*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 308*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 309*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 310*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 311*5113495bSYour Name 312*5113495bSYour Name #endif 313