1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _WBM2SW_COMPLETION_RING_TX_H_ 23 #define _WBM2SW_COMPLETION_RING_TX_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "tx_rate_stats_info.h" 28 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 29 30 struct wbm2sw_completion_ring_tx { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t buffer_virt_addr_31_0 : 32; 33 uint32_t buffer_virt_addr_63_32 : 32; 34 uint32_t release_source_module : 3, 35 cache_id : 1, 36 reserved_2a : 2, 37 buffer_or_desc_type : 3, 38 return_buffer_manager : 4, 39 tqm_release_reason : 4, 40 rbm_override_valid : 1, 41 sw_buffer_cookie_11_0 : 12, 42 cookie_conversion_status : 1, 43 wbm_internal_error : 1; 44 uint32_t tqm_status_number : 24, 45 transmit_count : 7, 46 sw_release_details_valid : 1; 47 uint32_t ack_frame_rssi : 8, 48 first_msdu : 1, 49 last_msdu : 1, 50 fw_tx_notify_frame : 3, 51 buffer_timestamp : 19; 52 struct tx_rate_stats_info tx_rate_stats; 53 uint32_t sw_peer_id : 16, 54 tid : 4, 55 sw_buffer_cookie_19_12 : 8, 56 looping_count : 4; 57 #else 58 uint32_t buffer_virt_addr_31_0 : 32; 59 uint32_t buffer_virt_addr_63_32 : 32; 60 uint32_t wbm_internal_error : 1, 61 cookie_conversion_status : 1, 62 sw_buffer_cookie_11_0 : 12, 63 rbm_override_valid : 1, 64 tqm_release_reason : 4, 65 return_buffer_manager : 4, 66 buffer_or_desc_type : 3, 67 reserved_2a : 2, 68 cache_id : 1, 69 release_source_module : 3; 70 uint32_t sw_release_details_valid : 1, 71 transmit_count : 7, 72 tqm_status_number : 24; 73 uint32_t buffer_timestamp : 19, 74 fw_tx_notify_frame : 3, 75 last_msdu : 1, 76 first_msdu : 1, 77 ack_frame_rssi : 8; 78 struct tx_rate_stats_info tx_rate_stats; 79 uint32_t looping_count : 4, 80 sw_buffer_cookie_19_12 : 8, 81 tid : 4, 82 sw_peer_id : 16; 83 #endif 84 }; 85 86 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 87 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 88 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 89 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 90 91 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 92 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 93 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 94 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 95 96 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 97 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 98 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 99 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 100 101 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 102 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 103 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 104 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 105 106 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 107 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 108 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 109 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 110 111 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 112 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 113 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 114 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 115 116 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 117 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 118 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 119 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 120 121 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 122 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 123 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 124 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 125 126 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 127 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 128 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 129 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 130 131 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 132 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 133 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 134 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 135 136 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 137 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 138 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 139 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 140 141 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 142 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 143 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 144 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 145 146 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 147 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 148 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 149 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 150 151 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 152 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 153 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 154 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 155 156 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 157 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 158 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 159 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 160 161 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 162 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 163 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 164 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 165 166 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 167 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 168 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 169 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 170 171 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 172 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 173 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 174 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 175 176 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 177 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 178 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 179 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 180 181 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 182 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 183 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 184 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 185 186 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 187 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 188 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 189 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 190 191 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 192 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 193 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 194 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 195 196 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 197 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 198 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 199 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 200 201 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 202 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 203 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 204 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 205 206 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 207 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 208 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 209 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 210 211 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 212 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 213 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 214 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 215 216 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 217 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 218 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 219 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 220 221 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 222 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 223 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 224 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 225 226 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 227 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 228 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 229 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 230 231 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 232 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 233 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 234 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 235 236 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 237 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 238 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 239 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 240 241 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 242 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 243 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 244 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff 245 246 #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c 247 #define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 248 #define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 249 #define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 250 251 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c 252 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 253 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 254 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 255 256 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 257 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 258 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 259 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 260 261 #endif 262