1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _WBM_RELEASE_RING_H_ 23 #define _WBM_RELEASE_RING_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "buffer_addr_info.h" 28 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 29 30 struct wbm_release_ring { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct buffer_addr_info released_buff_or_desc_addr_info; 33 uint32_t release_source_module : 3, 34 reserved_2a : 3, 35 buffer_or_desc_type : 3, 36 reserved_2b : 22, 37 wbm_internal_error : 1; 38 uint32_t reserved_3a : 32; 39 uint32_t reserved_4a : 32; 40 uint32_t reserved_5a : 32; 41 uint32_t reserved_6a : 32; 42 uint32_t reserved_7a : 28, 43 looping_count : 4; 44 #else 45 struct buffer_addr_info released_buff_or_desc_addr_info; 46 uint32_t wbm_internal_error : 1, 47 reserved_2b : 22, 48 buffer_or_desc_type : 3, 49 reserved_2a : 3, 50 release_source_module : 3; 51 uint32_t reserved_3a : 32; 52 uint32_t reserved_4a : 32; 53 uint32_t reserved_5a : 32; 54 uint32_t reserved_6a : 32; 55 uint32_t looping_count : 4, 56 reserved_7a : 28; 57 #endif 58 }; 59 60 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 61 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 62 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 63 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 64 65 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 66 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 67 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 68 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 69 70 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 71 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 72 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 73 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 74 75 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 76 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 77 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 78 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 79 80 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 81 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 82 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 83 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 84 85 #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 86 #define WBM_RELEASE_RING_RESERVED_2A_LSB 3 87 #define WBM_RELEASE_RING_RESERVED_2A_MSB 5 88 #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 89 90 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 91 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 92 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 93 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 94 95 #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 96 #define WBM_RELEASE_RING_RESERVED_2B_LSB 9 97 #define WBM_RELEASE_RING_RESERVED_2B_MSB 30 98 #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 99 100 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 101 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 102 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 103 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 104 105 #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c 106 #define WBM_RELEASE_RING_RESERVED_3A_LSB 0 107 #define WBM_RELEASE_RING_RESERVED_3A_MSB 31 108 #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff 109 110 #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 111 #define WBM_RELEASE_RING_RESERVED_4A_LSB 0 112 #define WBM_RELEASE_RING_RESERVED_4A_MSB 31 113 #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff 114 115 #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 116 #define WBM_RELEASE_RING_RESERVED_5A_LSB 0 117 #define WBM_RELEASE_RING_RESERVED_5A_MSB 31 118 #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff 119 120 #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 121 #define WBM_RELEASE_RING_RESERVED_6A_LSB 0 122 #define WBM_RELEASE_RING_RESERVED_6A_MSB 31 123 #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff 124 125 #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c 126 #define WBM_RELEASE_RING_RESERVED_7A_LSB 0 127 #define WBM_RELEASE_RING_RESERVED_7A_MSB 27 128 #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff 129 130 #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c 131 #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 132 #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 133 #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 134 135 #endif 136