1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _WBM_RELEASE_RING_RX_H_ 23 #define _WBM_RELEASE_RING_RX_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rx_msdu_desc_info.h" 28 #include "rx_mpdu_desc_info.h" 29 #include "buffer_addr_info.h" 30 #define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 31 32 struct wbm_release_ring_rx { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct buffer_addr_info released_buff_or_desc_addr_info; 35 uint32_t release_source_module : 3, 36 bm_action : 3, 37 buffer_or_desc_type : 3, 38 first_msdu_index : 4, 39 reserved_2a : 2, 40 cache_id : 1, 41 cookie_conversion_status : 1, 42 rxdma_push_reason : 2, 43 rxdma_error_code : 5, 44 reo_push_reason : 2, 45 reo_error_code : 5, 46 wbm_internal_error : 1; 47 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 48 struct rx_msdu_desc_info rx_msdu_desc_info_details; 49 uint32_t reserved_6a : 32; 50 uint32_t reserved_7a : 20, 51 ring_id : 8, 52 looping_count : 4; 53 #else 54 struct buffer_addr_info released_buff_or_desc_addr_info; 55 uint32_t wbm_internal_error : 1, 56 reo_error_code : 5, 57 reo_push_reason : 2, 58 rxdma_error_code : 5, 59 rxdma_push_reason : 2, 60 cookie_conversion_status : 1, 61 cache_id : 1, 62 reserved_2a : 2, 63 first_msdu_index : 4, 64 buffer_or_desc_type : 3, 65 bm_action : 3, 66 release_source_module : 3; 67 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 68 struct rx_msdu_desc_info rx_msdu_desc_info_details; 69 uint32_t reserved_6a : 32; 70 uint32_t looping_count : 4, 71 ring_id : 8, 72 reserved_7a : 20; 73 #endif 74 }; 75 76 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 77 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 78 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 79 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 80 81 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 82 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 83 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 84 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 85 86 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 87 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 88 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 89 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 90 91 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 92 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 93 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 94 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 95 96 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 97 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 98 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 99 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 100 101 #define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 102 #define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 103 #define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 104 #define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 105 106 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 107 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 108 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 109 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 110 111 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 112 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 113 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 114 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 115 116 #define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 117 #define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 118 #define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 119 #define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 120 121 #define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 122 #define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 123 #define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 124 #define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 125 126 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 127 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 128 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 129 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 130 131 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 132 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 133 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 134 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 135 136 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 137 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 138 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 139 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 140 141 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 142 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 143 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 144 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 145 146 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 147 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 148 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 149 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 150 151 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 152 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 153 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 154 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 155 156 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 157 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 158 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 159 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 160 161 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 162 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 163 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 164 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 165 166 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 167 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 168 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 169 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 170 171 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 172 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 173 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 174 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 175 176 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 177 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 178 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 179 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 180 181 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 182 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 183 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 184 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 185 186 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 187 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 188 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 189 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 190 191 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 192 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 193 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 194 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 195 196 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 197 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 198 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 199 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 200 201 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 202 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 203 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 204 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 205 206 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 207 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 208 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 209 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 210 211 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 212 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 213 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 214 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 215 216 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 217 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 218 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 219 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 220 221 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 222 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 223 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 224 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 225 226 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 227 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 228 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 229 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 230 231 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 232 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 233 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 234 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 235 236 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 237 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 238 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 239 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 240 241 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 242 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 243 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 244 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 245 246 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 247 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 248 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 249 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 250 251 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 252 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 253 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 254 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 255 256 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 257 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 258 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 259 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 260 261 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 262 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 263 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 264 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 265 266 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 267 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 268 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 269 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 270 271 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 272 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 273 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 274 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 275 276 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 277 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 278 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 279 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 280 281 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 282 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 283 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 284 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 285 286 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 287 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 288 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 289 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 290 291 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 292 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 293 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 294 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 295 296 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 297 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 298 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 299 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 300 301 #define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 302 #define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 303 #define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 304 #define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff 305 306 #define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c 307 #define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 308 #define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 309 #define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff 310 311 #define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c 312 #define WBM_RELEASE_RING_RX_RING_ID_LSB 20 313 #define WBM_RELEASE_RING_RX_RING_ID_MSB 27 314 #define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 315 316 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 317 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 318 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 319 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 320 321 #endif 322