1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _WBM_RELEASE_RING_TX_H_ 23 #define _WBM_RELEASE_RING_TX_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "tx_rate_stats_info.h" 28 #include "buffer_addr_info.h" 29 #define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 30 31 struct wbm_release_ring_tx { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 struct buffer_addr_info released_buff_or_desc_addr_info; 34 uint32_t release_source_module : 3, 35 bm_action : 3, 36 buffer_or_desc_type : 3, 37 first_msdu_index : 4, 38 tqm_release_reason : 4, 39 rbm_override_valid : 1, 40 rbm_override : 4, 41 reserved_2a : 7, 42 cache_id : 1, 43 cookie_conversion_status : 1, 44 wbm_internal_error : 1; 45 uint32_t tqm_status_number : 24, 46 transmit_count : 7, 47 sw_release_details_valid : 1; 48 uint32_t ack_frame_rssi : 8, 49 first_msdu : 1, 50 last_msdu : 1, 51 fw_tx_notify_frame : 3, 52 buffer_timestamp : 19; 53 struct tx_rate_stats_info tx_rate_stats; 54 uint32_t sw_peer_id : 16, 55 tid : 4, 56 tqm_status_number_31_24 : 8, 57 looping_count : 4; 58 #else 59 struct buffer_addr_info released_buff_or_desc_addr_info; 60 uint32_t wbm_internal_error : 1, 61 cookie_conversion_status : 1, 62 cache_id : 1, 63 reserved_2a : 7, 64 rbm_override : 4, 65 rbm_override_valid : 1, 66 tqm_release_reason : 4, 67 first_msdu_index : 4, 68 buffer_or_desc_type : 3, 69 bm_action : 3, 70 release_source_module : 3; 71 uint32_t sw_release_details_valid : 1, 72 transmit_count : 7, 73 tqm_status_number : 24; 74 uint32_t buffer_timestamp : 19, 75 fw_tx_notify_frame : 3, 76 last_msdu : 1, 77 first_msdu : 1, 78 ack_frame_rssi : 8; 79 struct tx_rate_stats_info tx_rate_stats; 80 uint32_t looping_count : 4, 81 tqm_status_number_31_24 : 8, 82 tid : 4, 83 sw_peer_id : 16; 84 #endif 85 }; 86 87 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 88 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 89 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 90 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 91 92 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 93 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 94 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 95 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 96 97 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 98 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 99 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 100 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 101 102 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 103 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 104 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 105 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 106 107 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 108 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 109 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 110 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 111 112 #define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 113 #define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 114 #define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 115 #define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 116 117 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 118 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 119 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 120 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 121 122 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 123 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 124 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 125 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 126 127 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 128 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 129 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 130 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 131 132 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 133 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 134 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 135 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 136 137 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 138 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 139 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 140 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 141 142 #define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 143 #define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 144 #define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 145 #define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 146 147 #define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 148 #define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 149 #define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 150 #define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 151 152 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 153 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 154 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 155 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 156 157 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 158 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 159 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 160 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 161 162 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 163 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 164 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 165 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 166 167 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 168 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 169 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 170 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 171 172 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 173 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 174 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 175 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 176 177 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 178 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 179 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 180 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 181 182 #define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 183 #define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 184 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 185 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 186 187 #define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 188 #define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 189 #define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 190 #define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 191 192 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 193 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 194 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 195 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 196 197 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 198 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 199 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 200 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 201 202 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 203 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 204 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 205 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 206 207 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 208 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 209 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 210 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 211 212 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 213 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 214 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 215 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 216 217 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 218 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 219 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 220 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 221 222 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 223 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 224 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 225 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 226 227 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 228 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 229 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 230 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 231 232 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 233 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 234 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 235 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 236 237 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 238 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 239 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 240 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 241 242 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 243 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 244 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 245 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 246 247 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 248 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 249 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 250 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 251 252 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 253 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 254 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 255 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 256 257 #define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 258 #define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 259 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 260 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff 261 262 #define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c 263 #define WBM_RELEASE_RING_TX_TID_LSB 16 264 #define WBM_RELEASE_RING_TX_TID_MSB 19 265 #define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 266 267 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c 268 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 269 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 270 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 271 272 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 273 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 274 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 275 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 276 277 #endif 278