1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _COEX_RX_STATUS_H_ 19 #define _COEX_RX_STATUS_H_ 20 21 #define NUM_OF_DWORDS_COEX_RX_STATUS 2 22 23 struct coex_rx_status { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t rx_mac_frame_status : 2, 26 rx_with_tx_response : 1, 27 rx_rate : 5, 28 rx_bw : 3, 29 single_mpdu : 1, 30 filter_status : 1, 31 ampdu : 1, 32 directed : 1, 33 reserved_0 : 1, 34 rx_nss : 3, 35 rx_rssi : 8, 36 rx_type : 3, 37 retry_bit_setting : 1, 38 more_data_bit_setting : 1; 39 uint32_t remain_rx_packet_time : 16, 40 rx_remaining_fes_time : 16; 41 #else 42 uint32_t more_data_bit_setting : 1, 43 retry_bit_setting : 1, 44 rx_type : 3, 45 rx_rssi : 8, 46 rx_nss : 3, 47 reserved_0 : 1, 48 directed : 1, 49 ampdu : 1, 50 filter_status : 1, 51 single_mpdu : 1, 52 rx_bw : 3, 53 rx_rate : 5, 54 rx_with_tx_response : 1, 55 rx_mac_frame_status : 2; 56 uint32_t rx_remaining_fes_time : 16, 57 remain_rx_packet_time : 16; 58 #endif 59 }; 60 61 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000 62 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 63 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 64 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003 65 66 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000 67 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 68 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 69 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004 70 71 #define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000 72 #define COEX_RX_STATUS_RX_RATE_LSB 3 73 #define COEX_RX_STATUS_RX_RATE_MSB 7 74 #define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8 75 76 #define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000 77 #define COEX_RX_STATUS_RX_BW_LSB 8 78 #define COEX_RX_STATUS_RX_BW_MSB 10 79 #define COEX_RX_STATUS_RX_BW_MASK 0x00000700 80 81 #define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000 82 #define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 83 #define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 84 #define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800 85 86 #define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000 87 #define COEX_RX_STATUS_FILTER_STATUS_LSB 12 88 #define COEX_RX_STATUS_FILTER_STATUS_MSB 12 89 #define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000 90 91 #define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000 92 #define COEX_RX_STATUS_AMPDU_LSB 13 93 #define COEX_RX_STATUS_AMPDU_MSB 13 94 #define COEX_RX_STATUS_AMPDU_MASK 0x00002000 95 96 #define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000 97 #define COEX_RX_STATUS_DIRECTED_LSB 14 98 #define COEX_RX_STATUS_DIRECTED_MSB 14 99 #define COEX_RX_STATUS_DIRECTED_MASK 0x00004000 100 101 #define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000 102 #define COEX_RX_STATUS_RESERVED_0_LSB 15 103 #define COEX_RX_STATUS_RESERVED_0_MSB 15 104 #define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000 105 106 #define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000 107 #define COEX_RX_STATUS_RX_NSS_LSB 16 108 #define COEX_RX_STATUS_RX_NSS_MSB 18 109 #define COEX_RX_STATUS_RX_NSS_MASK 0x00070000 110 111 #define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000 112 #define COEX_RX_STATUS_RX_RSSI_LSB 19 113 #define COEX_RX_STATUS_RX_RSSI_MSB 26 114 #define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000 115 116 #define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000 117 #define COEX_RX_STATUS_RX_TYPE_LSB 27 118 #define COEX_RX_STATUS_RX_TYPE_MSB 29 119 #define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000 120 121 #define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000 122 #define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 123 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 124 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000 125 126 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000 127 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 128 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 129 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000 130 131 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004 132 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0 133 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15 134 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff 135 136 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004 137 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16 138 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31 139 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000 140 141 #endif 142