xref: /wlan-driver/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _HE_SIG_A_MU_UL_INFO_H_
19 #define _HE_SIG_A_MU_UL_INFO_H_
20 
21 #define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
22 
23 struct he_sig_a_mu_ul_info {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t format_indication                                       :  1,
26                       bss_color_id                                            :  6,
27                       spatial_reuse                                           : 16,
28                       reserved_0a                                             :  1,
29                       transmit_bw                                             :  2,
30                       reserved_0b                                             :  6;
31              uint32_t txop_duration                                           :  7,
32                       reserved_1a                                             :  9,
33                       crc                                                     :  4,
34                       tail                                                    :  6,
35                       reserved_1b                                             :  5,
36                       rx_integrity_check_passed                               :  1;
37 #else
38              uint32_t reserved_0b                                             :  6,
39                       transmit_bw                                             :  2,
40                       reserved_0a                                             :  1,
41                       spatial_reuse                                           : 16,
42                       bss_color_id                                            :  6,
43                       format_indication                                       :  1;
44              uint32_t rx_integrity_check_passed                               :  1,
45                       reserved_1b                                             :  5,
46                       tail                                                    :  6,
47                       crc                                                     :  4,
48                       reserved_1a                                             :  9,
49                       txop_duration                                           :  7;
50 #endif
51 };
52 
53 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
54 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
55 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
56 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
57 
58 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
59 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
60 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
61 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
62 
63 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
64 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
65 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
66 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
67 
68 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
69 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
70 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
71 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
72 
73 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
74 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
75 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
76 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
77 
78 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
79 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
80 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
81 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
82 
83 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
84 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
85 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
86 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
87 
88 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
89 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
90 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
91 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
92 
93 #define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
94 #define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
95 #define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
96 #define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
97 
98 #define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
99 #define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
100 #define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
101 #define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
102 
103 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
104 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
105 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
106 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
107 
108 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
109 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
110 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
111 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
112 
113 #endif
114