xref: /wlan-driver/fw-api/hw/peach/v1/he_sig_b2_mu_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _HE_SIG_B2_MU_INFO_H_
19 #define _HE_SIG_B2_MU_INFO_H_
20 
21 #define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
22 
23 struct he_sig_b2_mu_info {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t sta_id                                                  : 11,
26                       sta_spatial_config                                      :  4,
27                       sta_mcs                                                 :  4,
28                       reserved_set_to_1                                       :  1,
29                       sta_coding                                              :  1,
30                       reserved_0a                                             :  7,
31                       nsts                                                    :  3,
32                       rx_integrity_check_passed                               :  1;
33              uint32_t user_order                                              :  8,
34                       cc_mask                                                 :  8,
35                       reserved_1a                                             : 16;
36 #else
37              uint32_t rx_integrity_check_passed                               :  1,
38                       nsts                                                    :  3,
39                       reserved_0a                                             :  7,
40                       sta_coding                                              :  1,
41                       reserved_set_to_1                                       :  1,
42                       sta_mcs                                                 :  4,
43                       sta_spatial_config                                      :  4,
44                       sta_id                                                  : 11;
45              uint32_t reserved_1a                                             : 16,
46                       cc_mask                                                 :  8,
47                       user_order                                              :  8;
48 #endif
49 };
50 
51 #define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
52 #define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
53 #define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
54 #define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
55 
56 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
57 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
58 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
59 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
60 
61 #define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
62 #define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
63 #define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
64 #define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
65 
66 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
67 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
68 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
69 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
70 
71 #define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
72 #define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
73 #define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
74 #define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
75 
76 #define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
77 #define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
78 #define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
79 #define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
80 
81 #define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
82 #define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
83 #define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
84 #define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
85 
86 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
87 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
88 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
89 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
90 
91 #define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
92 #define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
93 #define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
94 #define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
95 
96 #define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
97 #define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
98 #define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
99 #define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
100 
101 #define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
102 #define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
103 #define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
104 #define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
105 
106 #endif
107