1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _MACTX_PHY_DESC_H_ 19*5113495bSYour Name #define _MACTX_PHY_DESC_H_ 20*5113495bSYour Name 21*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_PHY_DESC 4 22*5113495bSYour Name 23*5113495bSYour Name struct mactx_phy_desc { 24*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25*5113495bSYour Name uint32_t reserved_0a : 16, 26*5113495bSYour Name bf_type : 2, 27*5113495bSYour Name wait_sifs : 2, 28*5113495bSYour Name dot11b_preamble_type : 1, 29*5113495bSYour Name pkt_type : 4, 30*5113495bSYour Name su_or_mu : 2, 31*5113495bSYour Name mu_type : 1, 32*5113495bSYour Name bandwidth : 3, 33*5113495bSYour Name channel_capture : 1; 34*5113495bSYour Name uint32_t mcs : 4, 35*5113495bSYour Name global_ofdma_mimo_enable : 1, 36*5113495bSYour Name reserved_1a : 1, 37*5113495bSYour Name stbc : 1, 38*5113495bSYour Name dot11ax_su_extended : 1, 39*5113495bSYour Name dot11ax_trigger_frame_embedded : 1, 40*5113495bSYour Name tx_pwr_shared : 8, 41*5113495bSYour Name tx_pwr_unshared : 8, 42*5113495bSYour Name measure_power : 1, 43*5113495bSYour Name tpc_glut_self_cal : 1, 44*5113495bSYour Name back_to_back_transmission_expected : 1, 45*5113495bSYour Name heavy_clip_nss : 3, 46*5113495bSYour Name txbf_per_packet_no_csd_no_walsh : 1; 47*5113495bSYour Name uint32_t ndp : 2, 48*5113495bSYour Name ul_flag : 1, 49*5113495bSYour Name triggered : 1, 50*5113495bSYour Name ap_pkt_bw : 3, 51*5113495bSYour Name ru_position_start : 8, 52*5113495bSYour Name pcu_ppdu_setup_start_reason : 3, 53*5113495bSYour Name tlv_source : 1, 54*5113495bSYour Name reserved_2a : 2, 55*5113495bSYour Name nss : 3, 56*5113495bSYour Name stream_offset : 3, 57*5113495bSYour Name reserved_2b : 2, 58*5113495bSYour Name clpc_enable : 1, 59*5113495bSYour Name mu_ndp : 1, 60*5113495bSYour Name response_expected : 1; 61*5113495bSYour Name uint32_t rx_chain_mask : 8, 62*5113495bSYour Name rx_chain_mask_valid : 1, 63*5113495bSYour Name ant_sel_valid : 1, 64*5113495bSYour Name ant_sel : 1, 65*5113495bSYour Name cp_setting : 2, 66*5113495bSYour Name he_ppdu_subtype : 2, 67*5113495bSYour Name active_channel : 3, 68*5113495bSYour Name generate_phyrx_tx_start_timing : 1, 69*5113495bSYour Name ltf_size : 2, 70*5113495bSYour Name ru_size_updated_v2 : 4, 71*5113495bSYour Name reserved_3c : 1, 72*5113495bSYour Name u_sig_puncture_pattern_encoding : 6; 73*5113495bSYour Name #else 74*5113495bSYour Name uint32_t channel_capture : 1, 75*5113495bSYour Name bandwidth : 3, 76*5113495bSYour Name mu_type : 1, 77*5113495bSYour Name su_or_mu : 2, 78*5113495bSYour Name pkt_type : 4, 79*5113495bSYour Name dot11b_preamble_type : 1, 80*5113495bSYour Name wait_sifs : 2, 81*5113495bSYour Name bf_type : 2, 82*5113495bSYour Name reserved_0a : 16; 83*5113495bSYour Name uint32_t txbf_per_packet_no_csd_no_walsh : 1, 84*5113495bSYour Name heavy_clip_nss : 3, 85*5113495bSYour Name back_to_back_transmission_expected : 1, 86*5113495bSYour Name tpc_glut_self_cal : 1, 87*5113495bSYour Name measure_power : 1, 88*5113495bSYour Name tx_pwr_unshared : 8, 89*5113495bSYour Name tx_pwr_shared : 8, 90*5113495bSYour Name dot11ax_trigger_frame_embedded : 1, 91*5113495bSYour Name dot11ax_su_extended : 1, 92*5113495bSYour Name stbc : 1, 93*5113495bSYour Name reserved_1a : 1, 94*5113495bSYour Name global_ofdma_mimo_enable : 1, 95*5113495bSYour Name mcs : 4; 96*5113495bSYour Name uint32_t response_expected : 1, 97*5113495bSYour Name mu_ndp : 1, 98*5113495bSYour Name clpc_enable : 1, 99*5113495bSYour Name reserved_2b : 2, 100*5113495bSYour Name stream_offset : 3, 101*5113495bSYour Name nss : 3, 102*5113495bSYour Name reserved_2a : 2, 103*5113495bSYour Name tlv_source : 1, 104*5113495bSYour Name pcu_ppdu_setup_start_reason : 3, 105*5113495bSYour Name ru_position_start : 8, 106*5113495bSYour Name ap_pkt_bw : 3, 107*5113495bSYour Name triggered : 1, 108*5113495bSYour Name ul_flag : 1, 109*5113495bSYour Name ndp : 2; 110*5113495bSYour Name uint32_t u_sig_puncture_pattern_encoding : 6, 111*5113495bSYour Name reserved_3c : 1, 112*5113495bSYour Name ru_size_updated_v2 : 4, 113*5113495bSYour Name ltf_size : 2, 114*5113495bSYour Name generate_phyrx_tx_start_timing : 1, 115*5113495bSYour Name active_channel : 3, 116*5113495bSYour Name he_ppdu_subtype : 2, 117*5113495bSYour Name cp_setting : 2, 118*5113495bSYour Name ant_sel : 1, 119*5113495bSYour Name ant_sel_valid : 1, 120*5113495bSYour Name rx_chain_mask_valid : 1, 121*5113495bSYour Name rx_chain_mask : 8; 122*5113495bSYour Name #endif 123*5113495bSYour Name }; 124*5113495bSYour Name 125*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000 126*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_LSB 0 127*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MSB 15 128*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff 129*5113495bSYour Name 130*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000 131*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_LSB 16 132*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MSB 17 133*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000 134*5113495bSYour Name 135*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000 136*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 137*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 138*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000 139*5113495bSYour Name 140*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000 141*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 142*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 143*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000 144*5113495bSYour Name 145*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000 146*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_LSB 21 147*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MSB 24 148*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000 149*5113495bSYour Name 150*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000 151*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_LSB 25 152*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MSB 26 153*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000 154*5113495bSYour Name 155*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000 156*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_LSB 27 157*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MSB 27 158*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000 159*5113495bSYour Name 160*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000 161*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_LSB 28 162*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MSB 30 163*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000 164*5113495bSYour Name 165*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000 166*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 167*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 168*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000 169*5113495bSYour Name 170*5113495bSYour Name #define MACTX_PHY_DESC_MCS_OFFSET 0x00000004 171*5113495bSYour Name #define MACTX_PHY_DESC_MCS_LSB 0 172*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MSB 3 173*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MASK 0x0000000f 174*5113495bSYour Name 175*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004 176*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4 177*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4 178*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010 179*5113495bSYour Name 180*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004 181*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_LSB 5 182*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MSB 5 183*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020 184*5113495bSYour Name 185*5113495bSYour Name #define MACTX_PHY_DESC_STBC_OFFSET 0x00000004 186*5113495bSYour Name #define MACTX_PHY_DESC_STBC_LSB 6 187*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MSB 6 188*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MASK 0x00000040 189*5113495bSYour Name 190*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 191*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7 192*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7 193*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080 194*5113495bSYour Name 195*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004 196*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8 197*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8 198*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100 199*5113495bSYour Name 200*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004 201*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9 202*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16 203*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00 204*5113495bSYour Name 205*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004 206*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17 207*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24 208*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000 209*5113495bSYour Name 210*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004 211*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_LSB 25 212*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MSB 25 213*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000 214*5113495bSYour Name 215*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004 216*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26 217*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26 218*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000 219*5113495bSYour Name 220*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004 221*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27 222*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27 223*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000 224*5113495bSYour Name 225*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004 226*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28 227*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30 228*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000 229*5113495bSYour Name 230*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004 231*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31 232*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31 233*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000 234*5113495bSYour Name 235*5113495bSYour Name #define MACTX_PHY_DESC_NDP_OFFSET 0x00000008 236*5113495bSYour Name #define MACTX_PHY_DESC_NDP_LSB 0 237*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MSB 1 238*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MASK 0x00000003 239*5113495bSYour Name 240*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008 241*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_LSB 2 242*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MSB 2 243*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004 244*5113495bSYour Name 245*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008 246*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_LSB 3 247*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MSB 3 248*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008 249*5113495bSYour Name 250*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008 251*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 252*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 253*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070 254*5113495bSYour Name 255*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008 256*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 257*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 258*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80 259*5113495bSYour Name 260*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008 261*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 262*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 263*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000 264*5113495bSYour Name 265*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008 266*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 267*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 268*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000 269*5113495bSYour Name 270*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008 271*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_LSB 19 272*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MSB 20 273*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000 274*5113495bSYour Name 275*5113495bSYour Name #define MACTX_PHY_DESC_NSS_OFFSET 0x00000008 276*5113495bSYour Name #define MACTX_PHY_DESC_NSS_LSB 21 277*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MSB 23 278*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MASK 0x00e00000 279*5113495bSYour Name 280*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008 281*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 282*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 283*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000 284*5113495bSYour Name 285*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008 286*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_LSB 27 287*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MSB 28 288*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000 289*5113495bSYour Name 290*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008 291*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 292*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 293*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000 294*5113495bSYour Name 295*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008 296*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_LSB 30 297*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MSB 30 298*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000 299*5113495bSYour Name 300*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008 301*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 302*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 303*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000 304*5113495bSYour Name 305*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c 306*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0 307*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7 308*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff 309*5113495bSYour Name 310*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c 311*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8 312*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8 313*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100 314*5113495bSYour Name 315*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c 316*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9 317*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9 318*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200 319*5113495bSYour Name 320*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c 321*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_LSB 10 322*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MSB 10 323*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400 324*5113495bSYour Name 325*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c 326*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_LSB 11 327*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MSB 12 328*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800 329*5113495bSYour Name 330*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c 331*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13 332*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14 333*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000 334*5113495bSYour Name 335*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c 336*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15 337*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17 338*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000 339*5113495bSYour Name 340*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c 341*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18 342*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18 343*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000 344*5113495bSYour Name 345*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c 346*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_LSB 19 347*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MSB 20 348*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000 349*5113495bSYour Name 350*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c 351*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21 352*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24 353*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000 354*5113495bSYour Name 355*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c 356*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_LSB 25 357*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MSB 25 358*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000 359*5113495bSYour Name 360*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c 361*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 362*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 363*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 364*5113495bSYour Name 365*5113495bSYour Name #endif 366