1 /* 2 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #ifndef __MSMHWIOBASE_H__ 17 #define __MSMHWIOBASE_H__ 18 19 #define WCSS_WCSS_BASE 0x00000000 20 #define WCSS_WCSS_BASE_SIZE 0x01000000 21 #define WCSS_WCSS_BASE_PHYS 0x00000000 22 23 #define QDSS_STM_SIZE_BASE 0x00100000 24 #define QDSS_STM_SIZE_BASE_SIZE 0x100000000 25 #define QDSS_STM_SIZE_BASE_PHYS 0x00100000 26 27 #define BOOT_ROM_SIZE_BASE 0x00200000 28 #define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 29 #define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 30 31 #define SYSTEM_IRAM_SIZE_BASE 0x00400000 32 #define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 33 #define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 34 35 #define BOOT_ROM_START_ADDRESS_BASE 0x01200000 36 #define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 37 #define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 38 39 #define BOOT_ROM_END_ADDRESS_BASE 0x013fffff 40 #define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 41 #define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff 42 43 #define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 44 #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 45 #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 46 47 #define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff 48 #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 49 #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff 50 51 #define QDSS_STM_BASE 0x01800000 52 #define QDSS_STM_BASE_SIZE 0x100000000 53 #define QDSS_STM_BASE_PHYS 0x01800000 54 55 #define QDSS_STM_END_BASE 0x018fffff 56 #define QDSS_STM_END_BASE_SIZE 0x100000000 57 #define QDSS_STM_END_BASE_PHYS 0x018fffff 58 59 #define TLMM_BASE 0x01900000 60 #define TLMM_BASE_SIZE 0x00200000 61 #define TLMM_BASE_PHYS 0x01900000 62 63 #define CORE_TOP_CSR_BASE 0x01b00000 64 #define CORE_TOP_CSR_BASE_SIZE 0x00040000 65 #define CORE_TOP_CSR_BASE_PHYS 0x01b00000 66 67 #define BLSP1_BLSP_BASE 0x01b40000 68 #define BLSP1_BLSP_BASE_SIZE 0x00040000 69 #define BLSP1_BLSP_BASE_PHYS 0x01b40000 70 71 #define SOC_WFSS_CE_REG_BASE 0x01b80000 72 #define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 73 #define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 74 75 #define WL_TLMM_BASE 0x01bc0000 76 #define WL_TLMM_BASE_SIZE 0x00020000 77 #define WL_TLMM_BASE_PHYS 0x01bc0000 78 79 #define MEMSS_CSR_BASE 0x01be0000 80 #define MEMSS_CSR_BASE_SIZE 0x0000001c 81 #define MEMSS_CSR_BASE_PHYS 0x01be0000 82 83 #define TSENS_SROT_BASE 0x01bf0000 84 #define TSENS_SROT_BASE_SIZE 0x00001000 85 #define TSENS_SROT_BASE_PHYS 0x01bf0000 86 87 #define TSENS_TM_BASE 0x01bf1000 88 #define TSENS_TM_BASE_SIZE 0x00001000 89 #define TSENS_TM_BASE_PHYS 0x01bf1000 90 91 #define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 92 #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 93 #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 94 95 #define QDSS_WRAPPER_TOP_BASE 0x01c80000 96 #define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd 97 #define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 98 99 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 100 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 101 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 102 103 #define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 104 #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 105 #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 106 107 #define SECURITY_CONTROL_WLAN_BASE 0x01e20000 108 #define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 109 #define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 110 111 #define EDPD_CAL_ACC_BASE 0x01e28000 112 #define EDPD_CAL_ACC_BASE_SIZE 0x00003000 113 #define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 114 115 #define CPR_CX_CPR3_BASE 0x01e30000 116 #define CPR_CX_CPR3_BASE_SIZE 0x00004000 117 #define CPR_CX_CPR3_BASE_PHYS 0x01e30000 118 119 #define CPR_MX_CPR3_BASE 0x01e34000 120 #define CPR_MX_CPR3_BASE_SIZE 0x00004000 121 #define CPR_MX_CPR3_BASE_PHYS 0x01e34000 122 123 #define GCC_GCC_BASE 0x01e40000 124 #define GCC_GCC_BASE_SIZE 0x000003e8 125 #define GCC_GCC_BASE_PHYS 0x01e40000 126 127 #define PRNG_PRNG_TOP_BASE 0x01e50000 128 #define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 129 #define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 130 131 #define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 132 #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 133 #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 134 135 #define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 136 #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 137 #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 138 139 #define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 140 #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 141 #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 142 143 #define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 144 #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 145 #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 146 147 #define RRI_PREFETCH_REG_BASE 0x01e70000 148 #define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 149 #define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 150 151 #define SYSTEM_NOC_BASE 0x01e80000 152 #define SYSTEM_NOC_BASE_SIZE 0x0000a000 153 #define SYSTEM_NOC_BASE_PHYS 0x01e80000 154 155 #define PC_NOC_BASE 0x01f00000 156 #define PC_NOC_BASE_SIZE 0x00003880 157 #define PC_NOC_BASE_PHYS 0x01f00000 158 159 #define WLAON_WL_AON_REG_BASE 0x01f80000 160 #define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 161 #define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 162 163 #define SYSPM_SYSPM_REG_BASE 0x01f82000 164 #define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 165 #define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 166 167 #define PMU_WLAN_PMU_TOP_BASE 0x01f88000 168 #define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 169 #define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 170 171 #define PMU_NOC_BASE 0x01f8a000 172 #define PMU_NOC_BASE_SIZE 0x00000080 173 #define PMU_NOC_BASE_PHYS 0x01f8a000 174 175 #define PCIE_ATU_REGION_BASE 0x04000000 176 #define PCIE_ATU_REGION_BASE_SIZE 0x100000000 177 #define PCIE_ATU_REGION_BASE_PHYS 0x04000000 178 179 #define PCIE_ATU_REGION_SIZE_BASE 0x40000000 180 #define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 181 #define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 182 183 #define PCIE_ATU_REGION_END_BASE 0x43ffffff 184 #define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 185 #define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff 186 187 #endif 188