1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _OFDMA_TRIGGER_DETAILS_H_ 19 #define _OFDMA_TRIGGER_DETAILS_H_ 20 21 #include "mlo_sta_id_details.h" 22 #define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 23 24 struct ofdma_trigger_details { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 uint32_t ax_trigger_source : 1, 27 rx_trigger_frame_user_source : 2, 28 received_bandwidth : 3, 29 txop_duration_all_ones : 1, 30 eht_trigger_response : 1, 31 pre_rssi_comb : 8, 32 rssi_comb : 8, 33 rxpcu_pcie_l0_req_duration : 8; 34 uint32_t he_trigger_ul_ppdu_length : 5, 35 he_trigger_ru_allocation : 8, 36 he_trigger_dl_tx_power : 5, 37 he_trigger_ul_target_rssi : 5, 38 he_trigger_ul_mcs : 2, 39 he_trigger_reserved : 1, 40 bss_color : 6; 41 uint32_t trigger_type : 4, 42 lsig_response_length : 12, 43 cascade_indication : 1, 44 carrier_sense : 1, 45 bandwidth : 2, 46 cp_ltf_size : 2, 47 mu_mimo_ltf_mode : 1, 48 number_of_ltfs : 3, 49 stbc : 1, 50 ldpc_extra_symbol : 1, 51 ap_tx_power_lsb_part : 4; 52 uint32_t ap_tx_power_msb_part : 2, 53 packet_extension_a_factor : 2, 54 packet_extension_pe_disambiguity : 1, 55 spatial_reuse : 16, 56 doppler : 1, 57 he_siga_reserved : 9, 58 reserved_3b : 1; 59 uint32_t aid12 : 12, 60 ru_allocation : 9, 61 mcs : 4, 62 dcm : 1, 63 start_spatial_stream : 3, 64 number_of_spatial_stream : 3; 65 uint32_t target_rssi : 7, 66 coding_type : 1, 67 mpdu_mu_spacing_factor : 2, 68 tid_aggregation_limit : 3, 69 reserved_5b : 1, 70 prefered_ac : 2, 71 bar_control_ack_policy : 1, 72 bar_control_multi_tid : 1, 73 bar_control_compressed_bitmap : 1, 74 bar_control_reserved : 9, 75 bar_control_tid_info : 4; 76 uint32_t nr0_per_tid_info_reserved : 12, 77 nr0_per_tid_info_tid_value : 4, 78 nr0_start_seq_ctrl_frag_number : 4, 79 nr0_start_seq_ctrl_start_seq_number : 12; 80 uint32_t nr1_per_tid_info_reserved : 12, 81 nr1_per_tid_info_tid_value : 4, 82 nr1_start_seq_ctrl_frag_number : 4, 83 nr1_start_seq_ctrl_start_seq_number : 12; 84 uint32_t nr2_per_tid_info_reserved : 12, 85 nr2_per_tid_info_tid_value : 4, 86 nr2_start_seq_ctrl_frag_number : 4, 87 nr2_start_seq_ctrl_start_seq_number : 12; 88 uint32_t nr3_per_tid_info_reserved : 12, 89 nr3_per_tid_info_tid_value : 4, 90 nr3_start_seq_ctrl_frag_number : 4, 91 nr3_start_seq_ctrl_start_seq_number : 12; 92 uint32_t nr4_per_tid_info_reserved : 12, 93 nr4_per_tid_info_tid_value : 4, 94 nr4_start_seq_ctrl_frag_number : 4, 95 nr4_start_seq_ctrl_start_seq_number : 12; 96 uint32_t nr5_per_tid_info_reserved : 12, 97 nr5_per_tid_info_tid_value : 4, 98 nr5_start_seq_ctrl_frag_number : 4, 99 nr5_start_seq_ctrl_start_seq_number : 12; 100 uint32_t nr6_per_tid_info_reserved : 12, 101 nr6_per_tid_info_tid_value : 4, 102 nr6_start_seq_ctrl_frag_number : 4, 103 nr6_start_seq_ctrl_start_seq_number : 12; 104 uint32_t nr7_per_tid_info_reserved : 12, 105 nr7_per_tid_info_tid_value : 4, 106 nr7_start_seq_ctrl_frag_number : 4, 107 nr7_start_seq_ctrl_start_seq_number : 12; 108 uint32_t fb_segment_retransmission_bitmap : 8, 109 reserved_14a : 2, 110 u_sig_puncture_pattern_encoding : 6, 111 dot11be_puncture_bitmap : 16; 112 uint32_t rx_chain_mask : 8, 113 rx_duration_field : 16, 114 scrambler_seed : 7, 115 rx_chain_mask_type : 1; 116 struct mlo_sta_id_details mlo_sta_id_details_rx; 117 uint16_t normalized_pre_rssi_comb : 8, 118 normalized_rssi_comb : 8; 119 uint32_t sw_peer_id : 16, 120 response_tx_duration : 16; 121 uint32_t __reserved_g_0005_trigger_subtype : 4, 122 tbr_trigger_common_info_79_68 : 12, 123 tbr_trigger_sound_reserved_20_12 : 9, 124 i2r_rep : 3, 125 tbr_trigger_sound_reserved_25_24 : 2, 126 reserved_18a : 1, 127 qos_null_only_response_tx : 1; 128 uint32_t tbr_trigger_sound_sac : 16, 129 reserved_19a : 8, 130 u_sig_reserved2 : 5, 131 reserved_19b : 3; 132 uint32_t eht_special_aid12 : 12, 133 phy_version : 3, 134 bandwidth_ext : 2, 135 eht_spatial_reuse : 8, 136 u_sig_reserved1 : 7; 137 uint32_t eht_trigger_special_user_info_71_40 : 32; 138 #else 139 uint32_t rxpcu_pcie_l0_req_duration : 8, 140 rssi_comb : 8, 141 pre_rssi_comb : 8, 142 eht_trigger_response : 1, 143 txop_duration_all_ones : 1, 144 received_bandwidth : 3, 145 rx_trigger_frame_user_source : 2, 146 ax_trigger_source : 1; 147 uint32_t bss_color : 6, 148 he_trigger_reserved : 1, 149 he_trigger_ul_mcs : 2, 150 he_trigger_ul_target_rssi : 5, 151 he_trigger_dl_tx_power : 5, 152 he_trigger_ru_allocation : 8, 153 he_trigger_ul_ppdu_length : 5; 154 uint32_t ap_tx_power_lsb_part : 4, 155 ldpc_extra_symbol : 1, 156 stbc : 1, 157 number_of_ltfs : 3, 158 mu_mimo_ltf_mode : 1, 159 cp_ltf_size : 2, 160 bandwidth : 2, 161 carrier_sense : 1, 162 cascade_indication : 1, 163 lsig_response_length : 12, 164 trigger_type : 4; 165 uint32_t reserved_3b : 1, 166 he_siga_reserved : 9, 167 doppler : 1, 168 spatial_reuse : 16, 169 packet_extension_pe_disambiguity : 1, 170 packet_extension_a_factor : 2, 171 ap_tx_power_msb_part : 2; 172 uint32_t number_of_spatial_stream : 3, 173 start_spatial_stream : 3, 174 dcm : 1, 175 mcs : 4, 176 ru_allocation : 9, 177 aid12 : 12; 178 uint32_t bar_control_tid_info : 4, 179 bar_control_reserved : 9, 180 bar_control_compressed_bitmap : 1, 181 bar_control_multi_tid : 1, 182 bar_control_ack_policy : 1, 183 prefered_ac : 2, 184 reserved_5b : 1, 185 tid_aggregation_limit : 3, 186 mpdu_mu_spacing_factor : 2, 187 coding_type : 1, 188 target_rssi : 7; 189 uint32_t nr0_start_seq_ctrl_start_seq_number : 12, 190 nr0_start_seq_ctrl_frag_number : 4, 191 nr0_per_tid_info_tid_value : 4, 192 nr0_per_tid_info_reserved : 12; 193 uint32_t nr1_start_seq_ctrl_start_seq_number : 12, 194 nr1_start_seq_ctrl_frag_number : 4, 195 nr1_per_tid_info_tid_value : 4, 196 nr1_per_tid_info_reserved : 12; 197 uint32_t nr2_start_seq_ctrl_start_seq_number : 12, 198 nr2_start_seq_ctrl_frag_number : 4, 199 nr2_per_tid_info_tid_value : 4, 200 nr2_per_tid_info_reserved : 12; 201 uint32_t nr3_start_seq_ctrl_start_seq_number : 12, 202 nr3_start_seq_ctrl_frag_number : 4, 203 nr3_per_tid_info_tid_value : 4, 204 nr3_per_tid_info_reserved : 12; 205 uint32_t nr4_start_seq_ctrl_start_seq_number : 12, 206 nr4_start_seq_ctrl_frag_number : 4, 207 nr4_per_tid_info_tid_value : 4, 208 nr4_per_tid_info_reserved : 12; 209 uint32_t nr5_start_seq_ctrl_start_seq_number : 12, 210 nr5_start_seq_ctrl_frag_number : 4, 211 nr5_per_tid_info_tid_value : 4, 212 nr5_per_tid_info_reserved : 12; 213 uint32_t nr6_start_seq_ctrl_start_seq_number : 12, 214 nr6_start_seq_ctrl_frag_number : 4, 215 nr6_per_tid_info_tid_value : 4, 216 nr6_per_tid_info_reserved : 12; 217 uint32_t nr7_start_seq_ctrl_start_seq_number : 12, 218 nr7_start_seq_ctrl_frag_number : 4, 219 nr7_per_tid_info_tid_value : 4, 220 nr7_per_tid_info_reserved : 12; 221 uint32_t dot11be_puncture_bitmap : 16, 222 u_sig_puncture_pattern_encoding : 6, 223 reserved_14a : 2, 224 fb_segment_retransmission_bitmap : 8; 225 uint32_t rx_chain_mask_type : 1, 226 scrambler_seed : 7, 227 rx_duration_field : 16, 228 rx_chain_mask : 8; 229 uint32_t normalized_rssi_comb : 8, 230 normalized_pre_rssi_comb : 8; 231 struct mlo_sta_id_details mlo_sta_id_details_rx; 232 uint32_t response_tx_duration : 16, 233 sw_peer_id : 16; 234 uint32_t qos_null_only_response_tx : 1, 235 reserved_18a : 1, 236 tbr_trigger_sound_reserved_25_24 : 2, 237 i2r_rep : 3, 238 tbr_trigger_sound_reserved_20_12 : 9, 239 tbr_trigger_common_info_79_68 : 12, 240 __reserved_g_0005_trigger_subtype : 4; 241 uint32_t reserved_19b : 3, 242 u_sig_reserved2 : 5, 243 reserved_19a : 8, 244 tbr_trigger_sound_sac : 16; 245 uint32_t u_sig_reserved1 : 7, 246 eht_spatial_reuse : 8, 247 bandwidth_ext : 2, 248 phy_version : 3, 249 eht_special_aid12 : 12; 250 uint32_t eht_trigger_special_user_info_71_40 : 32; 251 #endif 252 }; 253 254 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 255 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 256 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 257 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000001 258 259 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x00000000 260 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 261 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 262 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x00000006 263 264 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x00000000 265 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 266 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 267 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x00000038 268 269 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x00000000 270 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 271 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 272 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x00000040 273 274 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x00000000 275 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 276 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 277 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x00000080 278 279 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x00000000 280 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 281 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 282 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x0000ff00 283 284 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x00000000 285 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 286 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 287 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x00ff0000 288 289 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x00000000 290 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 291 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 292 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0xff000000 293 294 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x00000004 295 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 0 296 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 4 297 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f 298 299 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x00000004 300 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 5 301 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 12 302 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe0 303 304 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x00000004 305 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 13 306 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 17 307 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e000 308 309 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x00000004 310 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 18 311 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 22 312 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c0000 313 314 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x00000004 315 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 23 316 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 24 317 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x01800000 318 319 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x00000004 320 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 25 321 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 25 322 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x02000000 323 324 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x00000004 325 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 26 326 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 31 327 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc000000 328 329 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000008 330 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 331 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 332 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f 333 334 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000008 335 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 336 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 337 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0000fff0 338 339 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x00000008 340 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 341 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 342 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x00010000 343 344 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x00000008 345 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 346 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 347 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x00020000 348 349 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x00000008 350 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 351 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 352 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x000c0000 353 354 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x00000008 355 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 356 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 357 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x00300000 358 359 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x00000008 360 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 361 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 362 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x00400000 363 364 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x00000008 365 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 366 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 367 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x03800000 368 369 #define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x00000008 370 #define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 371 #define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 372 #define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x04000000 373 374 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 375 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 376 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 377 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x08000000 378 379 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x00000008 380 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 381 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 382 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0xf0000000 383 384 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000c 385 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 0 386 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 1 387 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x00000003 388 389 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000c 390 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 2 391 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 3 392 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c 393 394 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000c 395 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 4 396 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 4 397 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000010 398 399 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000c 400 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 5 401 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 20 402 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe0 403 404 #define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000c 405 #define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 21 406 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 21 407 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x00200000 408 409 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000c 410 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 22 411 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 30 412 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc00000 413 414 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000c 415 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 31 416 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 31 417 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x80000000 418 419 #define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x00000010 420 #define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 421 #define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 422 #define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x00000fff 423 424 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x00000010 425 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 426 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 427 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x001ff000 428 429 #define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x00000010 430 #define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 431 #define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 432 #define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x01e00000 433 434 #define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x00000010 435 #define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 436 #define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 437 #define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x02000000 438 439 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x00000010 440 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 441 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 442 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x1c000000 443 444 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x00000010 445 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 446 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 447 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0xe0000000 448 449 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x00000014 450 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 0 451 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 6 452 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f 453 454 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x00000014 455 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 7 456 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 7 457 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x00000080 458 459 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x00000014 460 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 8 461 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 9 462 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x00000300 463 464 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x00000014 465 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 10 466 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 12 467 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c00 468 469 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x00000014 470 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 13 471 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 13 472 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x00002000 473 474 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x00000014 475 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 14 476 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 15 477 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c000 478 479 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x00000014 480 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 16 481 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 16 482 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x00010000 483 484 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x00000014 485 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 17 486 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 17 487 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x00020000 488 489 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x00000014 490 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 18 491 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 18 492 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x00040000 493 494 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x00000014 495 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 19 496 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 27 497 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff80000 498 499 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x00000014 500 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 28 501 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 31 502 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf0000000 503 504 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x00000018 505 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 506 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 507 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x00000fff 508 509 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x00000018 510 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 511 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 512 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 513 514 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000018 515 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 516 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 517 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 518 519 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000018 520 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 521 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 522 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 523 524 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000001c 525 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 0 526 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 11 527 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff 528 529 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000001c 530 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 12 531 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 15 532 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 533 534 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000001c 535 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 536 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 537 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 538 539 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000001c 540 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 541 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 542 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 543 544 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x00000020 545 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 546 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 547 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x00000fff 548 549 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x00000020 550 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 551 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 552 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 553 554 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000020 555 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 556 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 557 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 558 559 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000020 560 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 561 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 562 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 563 564 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x00000024 565 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 0 566 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 11 567 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff 568 569 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x00000024 570 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 12 571 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 15 572 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 573 574 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000024 575 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 576 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 577 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 578 579 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000024 580 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 581 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 582 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 583 584 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x00000028 585 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 586 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 587 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x00000fff 588 589 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x00000028 590 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 591 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 592 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 593 594 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000028 595 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 596 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 597 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 598 599 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000028 600 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 601 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 602 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 603 604 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000002c 605 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 0 606 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 11 607 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff 608 609 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000002c 610 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 12 611 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 15 612 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 613 614 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000002c 615 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 616 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 617 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 618 619 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000002c 620 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 621 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 622 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 623 624 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x00000030 625 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 626 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 627 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x00000fff 628 629 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x00000030 630 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 631 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 632 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 633 634 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000030 635 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 636 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 637 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 638 639 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000030 640 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 641 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 642 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 643 644 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x00000034 645 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 0 646 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 11 647 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff 648 649 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x00000034 650 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 12 651 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 15 652 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 653 654 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000034 655 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 656 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 657 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 658 659 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000034 660 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 661 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 662 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 663 664 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x00000038 665 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 666 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 667 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x000000ff 668 669 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x00000038 670 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 671 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 672 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x00000300 673 674 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000038 675 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 676 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 677 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000fc00 678 679 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000038 680 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 681 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 682 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0xffff0000 683 684 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000003c 685 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 0 686 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 7 687 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff 688 689 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000003c 690 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 8 691 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 23 692 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff00 693 694 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000003c 695 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 24 696 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 30 697 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f000000 698 699 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000003c 700 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 31 701 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 31 702 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x80000000 703 704 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000040 705 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 706 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 707 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff 708 709 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000040 710 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 711 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 712 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 713 714 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000040 715 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 716 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 717 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 718 719 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000040 720 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 721 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 722 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 723 724 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000040 725 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 726 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 727 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 728 729 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000040 730 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 731 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 732 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 733 734 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x00000040 735 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 736 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 737 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0xff000000 738 739 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x00000044 740 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 741 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 742 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff 743 744 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x00000044 745 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 16 746 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 31 747 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff0000 748 749 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000048 750 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 751 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 752 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x0000000f 753 754 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x00000048 755 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 756 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 757 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x0000fff0 758 759 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x00000048 760 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 761 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 762 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x01ff0000 763 764 #define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x00000048 765 #define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 766 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 767 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x0e000000 768 769 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x00000048 770 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 771 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 772 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x30000000 773 774 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x00000048 775 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 776 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 777 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x40000000 778 779 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x00000048 780 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 781 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 782 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x80000000 783 784 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000004c 785 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 0 786 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 15 787 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff 788 789 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000004c 790 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 16 791 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 23 792 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff0000 793 794 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000004c 795 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 24 796 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 28 797 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f000000 798 799 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000004c 800 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 29 801 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 31 802 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe0000000 803 804 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x00000050 805 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 806 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 807 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x00000fff 808 809 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x00000050 810 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 811 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 812 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x00007000 813 814 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x00000050 815 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 816 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 817 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x00018000 818 819 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x00000050 820 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 821 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 822 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x01fe0000 823 824 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x00000050 825 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 826 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 827 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0xfe000000 828 829 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x00000054 830 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 0 831 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 31 832 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff 833 834 #endif 835