1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ 19 #define _RECEIVED_TRIGGER_INFO_DETAILS_H_ 20 21 #define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 22 23 struct received_trigger_info_details { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t trigger_type : 4, 26 ax_trigger_source : 1, 27 ax_trigger_type : 4, 28 trigger_source_sta_full_aid : 13, 29 frame_control_valid : 1, 30 qos_control_valid : 1, 31 he_control_info_valid : 1, 32 __reserved_g_0005_trigger_subtype : 4, 33 txop_sharing_mode : 2, 34 tid_aggregation_limit_is_zero : 1; 35 uint32_t phy_ppdu_id : 16, 36 lsig_response_length : 12, 37 reserved_1a : 4; 38 uint32_t frame_control : 16, 39 qos_control : 16; 40 uint32_t sw_peer_id : 16, 41 txop_sharing_allocation_duration : 9, 42 reserved_3a : 7; 43 uint32_t he_control : 32; 44 #else 45 uint32_t tid_aggregation_limit_is_zero : 1, 46 txop_sharing_mode : 2, 47 __reserved_g_0005_trigger_subtype : 4, 48 he_control_info_valid : 1, 49 qos_control_valid : 1, 50 frame_control_valid : 1, 51 trigger_source_sta_full_aid : 13, 52 ax_trigger_type : 4, 53 ax_trigger_source : 1, 54 trigger_type : 4; 55 uint32_t reserved_1a : 4, 56 lsig_response_length : 12, 57 phy_ppdu_id : 16; 58 uint32_t qos_control : 16, 59 frame_control : 16; 60 uint32_t reserved_3a : 7, 61 txop_sharing_allocation_duration : 9, 62 sw_peer_id : 16; 63 uint32_t he_control : 32; 64 #endif 65 }; 66 67 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 68 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 69 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 70 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f 71 72 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 73 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 74 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 75 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 76 77 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 78 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 79 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 80 #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 81 82 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 83 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 84 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 85 #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 86 87 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 88 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 89 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 90 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 91 92 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 93 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 94 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 95 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 96 97 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 98 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 99 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 100 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 101 102 #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 103 #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 104 #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 105 #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 106 107 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 108 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 109 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 110 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 111 112 #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 113 #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 114 #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 115 #define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 116 117 #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 118 #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 119 #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 120 #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff 121 122 #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 123 #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 124 #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 125 #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 126 127 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 128 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 129 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 130 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 131 132 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 133 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 134 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 135 #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff 136 137 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 138 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 139 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 140 #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 141 142 #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c 143 #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 144 #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 145 #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff 146 147 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c 148 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 149 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 150 #define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 151 152 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c 153 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25 154 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 155 #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000 156 157 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 158 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 159 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 160 #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff 161 162 #endif 163