1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _REO_FLUSH_CACHE_H_ 19 #define _REO_FLUSH_CACHE_H_ 20 21 #include "uniform_reo_cmd_header.h" 22 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 23 24 struct reo_flush_cache { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct uniform_reo_cmd_header cmd_header; 27 uint32_t flush_addr_31_0 : 32; 28 uint32_t flush_addr_39_32 : 8, 29 forward_all_mpdus_in_queue : 1, 30 release_cache_block_index : 1, 31 cache_block_resource_index : 2, 32 flush_without_invalidate : 1, 33 block_cache_usage_after_flush : 1, 34 flush_entire_cache : 1, 35 flush_queue_1k_desc : 1, 36 reserved_2b : 16; 37 uint32_t reserved_3a : 32; 38 uint32_t reserved_4a : 32; 39 uint32_t reserved_5a : 32; 40 uint32_t reserved_6a : 32; 41 uint32_t reserved_7a : 32; 42 uint32_t reserved_8a : 32; 43 #else 44 struct uniform_reo_cmd_header cmd_header; 45 uint32_t flush_addr_31_0 : 32; 46 uint32_t reserved_2b : 16, 47 flush_queue_1k_desc : 1, 48 flush_entire_cache : 1, 49 block_cache_usage_after_flush : 1, 50 flush_without_invalidate : 1, 51 cache_block_resource_index : 2, 52 release_cache_block_index : 1, 53 forward_all_mpdus_in_queue : 1, 54 flush_addr_39_32 : 8; 55 uint32_t reserved_3a : 32; 56 uint32_t reserved_4a : 32; 57 uint32_t reserved_5a : 32; 58 uint32_t reserved_6a : 32; 59 uint32_t reserved_7a : 32; 60 uint32_t reserved_8a : 32; 61 #endif 62 }; 63 64 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 65 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 66 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 67 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 68 69 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 70 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 71 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 72 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 73 74 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 75 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 76 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 77 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 78 79 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x00000004 80 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 0 81 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 31 82 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff 83 84 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x00000008 85 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 86 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 87 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x000000ff 88 89 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 90 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 91 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 92 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 93 94 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 95 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 96 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 97 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 98 99 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 100 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 101 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 102 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 103 104 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 105 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 106 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 107 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 108 109 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 110 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 111 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 112 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 113 114 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 115 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 116 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 117 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x00004000 118 119 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x00000008 120 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 121 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 122 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x00008000 123 124 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x00000008 125 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 126 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 127 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0xffff0000 128 129 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000c 130 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 0 131 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 31 132 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff 133 134 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x00000010 135 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 136 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 137 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0xffffffff 138 139 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x00000014 140 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 0 141 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 31 142 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff 143 144 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x00000018 145 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 146 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 147 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0xffffffff 148 149 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000001c 150 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 0 151 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 31 152 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff 153 154 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x00000020 155 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 156 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 157 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0xffffffff 158 159 #endif 160