xref: /wlan-driver/fw-api/hw/peach/v1/reo_flush_cache_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1*5113495bSYour Name /*
2*5113495bSYour Name  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name 
18*5113495bSYour Name #ifndef _REO_FLUSH_CACHE_STATUS_H_
19*5113495bSYour Name #define _REO_FLUSH_CACHE_STATUS_H_
20*5113495bSYour Name 
21*5113495bSYour Name #include "uniform_reo_status_header.h"
22*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27
23*5113495bSYour Name 
24*5113495bSYour Name struct reo_flush_cache_status {
25*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
26*5113495bSYour Name              uint32_t tlv32_ring_padding                                      : 32;
27*5113495bSYour Name              struct   uniform_reo_status_header                                 status_header;
28*5113495bSYour Name              uint32_t error_detected                                          :  1,
29*5113495bSYour Name                       block_error_details                                     :  2,
30*5113495bSYour Name                       reserved_2a                                             :  5,
31*5113495bSYour Name                       cache_controller_flush_status_hit                       :  1,
32*5113495bSYour Name                       cache_controller_flush_status_desc_type                 :  3,
33*5113495bSYour Name                       cache_controller_flush_status_client_id                 :  4,
34*5113495bSYour Name                       cache_controller_flush_status_error                     :  2,
35*5113495bSYour Name                       cache_controller_flush_count                            :  8,
36*5113495bSYour Name                       flush_queue_1k_desc                                     :  1,
37*5113495bSYour Name                       reserved_2b                                             :  5;
38*5113495bSYour Name              uint32_t reserved_3a                                             : 32;
39*5113495bSYour Name              uint32_t reserved_4a                                             : 32;
40*5113495bSYour Name              uint32_t reserved_5a                                             : 32;
41*5113495bSYour Name              uint32_t reserved_6a                                             : 32;
42*5113495bSYour Name              uint32_t reserved_7a                                             : 32;
43*5113495bSYour Name              uint32_t reserved_8a                                             : 32;
44*5113495bSYour Name              uint32_t reserved_9a                                             : 32;
45*5113495bSYour Name              uint32_t reserved_10a                                            : 32;
46*5113495bSYour Name              uint32_t reserved_11a                                            : 32;
47*5113495bSYour Name              uint32_t reserved_12a                                            : 32;
48*5113495bSYour Name              uint32_t reserved_13a                                            : 32;
49*5113495bSYour Name              uint32_t reserved_14a                                            : 32;
50*5113495bSYour Name              uint32_t reserved_15a                                            : 32;
51*5113495bSYour Name              uint32_t reserved_16a                                            : 32;
52*5113495bSYour Name              uint32_t reserved_17a                                            : 32;
53*5113495bSYour Name              uint32_t reserved_18a                                            : 32;
54*5113495bSYour Name              uint32_t reserved_19a                                            : 32;
55*5113495bSYour Name              uint32_t reserved_20a                                            : 32;
56*5113495bSYour Name              uint32_t reserved_21a                                            : 32;
57*5113495bSYour Name              uint32_t reserved_22a                                            : 32;
58*5113495bSYour Name              uint32_t reserved_23a                                            : 32;
59*5113495bSYour Name              uint32_t reserved_24a                                            : 32;
60*5113495bSYour Name              uint32_t reserved_25a                                            : 28,
61*5113495bSYour Name                       looping_count                                           :  4;
62*5113495bSYour Name #else
63*5113495bSYour Name              uint32_t tlv32_ring_padding                                      : 32;
64*5113495bSYour Name              struct   uniform_reo_status_header                                 status_header;
65*5113495bSYour Name              uint32_t reserved_2b                                             :  5,
66*5113495bSYour Name                       flush_queue_1k_desc                                     :  1,
67*5113495bSYour Name                       cache_controller_flush_count                            :  8,
68*5113495bSYour Name                       cache_controller_flush_status_error                     :  2,
69*5113495bSYour Name                       cache_controller_flush_status_client_id                 :  4,
70*5113495bSYour Name                       cache_controller_flush_status_desc_type                 :  3,
71*5113495bSYour Name                       cache_controller_flush_status_hit                       :  1,
72*5113495bSYour Name                       reserved_2a                                             :  5,
73*5113495bSYour Name                       block_error_details                                     :  2,
74*5113495bSYour Name                       error_detected                                          :  1;
75*5113495bSYour Name              uint32_t reserved_3a                                             : 32;
76*5113495bSYour Name              uint32_t reserved_4a                                             : 32;
77*5113495bSYour Name              uint32_t reserved_5a                                             : 32;
78*5113495bSYour Name              uint32_t reserved_6a                                             : 32;
79*5113495bSYour Name              uint32_t reserved_7a                                             : 32;
80*5113495bSYour Name              uint32_t reserved_8a                                             : 32;
81*5113495bSYour Name              uint32_t reserved_9a                                             : 32;
82*5113495bSYour Name              uint32_t reserved_10a                                            : 32;
83*5113495bSYour Name              uint32_t reserved_11a                                            : 32;
84*5113495bSYour Name              uint32_t reserved_12a                                            : 32;
85*5113495bSYour Name              uint32_t reserved_13a                                            : 32;
86*5113495bSYour Name              uint32_t reserved_14a                                            : 32;
87*5113495bSYour Name              uint32_t reserved_15a                                            : 32;
88*5113495bSYour Name              uint32_t reserved_16a                                            : 32;
89*5113495bSYour Name              uint32_t reserved_17a                                            : 32;
90*5113495bSYour Name              uint32_t reserved_18a                                            : 32;
91*5113495bSYour Name              uint32_t reserved_19a                                            : 32;
92*5113495bSYour Name              uint32_t reserved_20a                                            : 32;
93*5113495bSYour Name              uint32_t reserved_21a                                            : 32;
94*5113495bSYour Name              uint32_t reserved_22a                                            : 32;
95*5113495bSYour Name              uint32_t reserved_23a                                            : 32;
96*5113495bSYour Name              uint32_t reserved_24a                                            : 32;
97*5113495bSYour Name              uint32_t looping_count                                           :  4,
98*5113495bSYour Name                       reserved_25a                                            : 28;
99*5113495bSYour Name #endif
100*5113495bSYour Name };
101*5113495bSYour Name 
102*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET                            0x00000000
103*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB                               0
104*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB                               31
105*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK                              0xffffffff
106*5113495bSYour Name 
107*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x00000004
108*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
109*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
110*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x0000ffff
111*5113495bSYour Name 
112*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x00000004
113*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
114*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
115*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x03ff0000
116*5113495bSYour Name 
117*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x00000004
118*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
119*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
120*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x0c000000
121*5113495bSYour Name 
122*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x00000004
123*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
124*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
125*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0xf0000000
126*5113495bSYour Name 
127*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x00000008
128*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          0
129*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          31
130*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff
131*5113495bSYour Name 
132*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000c
133*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB                                   0
134*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB                                   0
135*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK                                  0x00000001
136*5113495bSYour Name 
137*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET                           0x0000000c
138*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB                              1
139*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB                              2
140*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK                             0x00000006
141*5113495bSYour Name 
142*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET                                   0x0000000c
143*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB                                      3
144*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB                                      7
145*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK                                     0x000000f8
146*5113495bSYour Name 
147*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET             0x0000000c
148*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB                8
149*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB                8
150*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK               0x00000100
151*5113495bSYour Name 
152*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET       0x0000000c
153*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB          9
154*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB          11
155*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK         0x00000e00
156*5113495bSYour Name 
157*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET       0x0000000c
158*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB          12
159*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB          15
160*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK         0x0000f000
161*5113495bSYour Name 
162*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET           0x0000000c
163*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB              16
164*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB              17
165*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK             0x00030000
166*5113495bSYour Name 
167*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET                  0x0000000c
168*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB                     18
169*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB                     25
170*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK                    0x03fc0000
171*5113495bSYour Name 
172*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET                           0x0000000c
173*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB                              26
174*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB                              26
175*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK                             0x04000000
176*5113495bSYour Name 
177*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET                                   0x0000000c
178*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB                                      27
179*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB                                      31
180*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK                                     0xf8000000
181*5113495bSYour Name 
182*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET                                   0x00000010
183*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB                                      0
184*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB                                      31
185*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK                                     0xffffffff
186*5113495bSYour Name 
187*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET                                   0x00000014
188*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB                                      0
189*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB                                      31
190*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK                                     0xffffffff
191*5113495bSYour Name 
192*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET                                   0x00000018
193*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB                                      0
194*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB                                      31
195*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK                                     0xffffffff
196*5113495bSYour Name 
197*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET                                   0x0000001c
198*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB                                      0
199*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB                                      31
200*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK                                     0xffffffff
201*5113495bSYour Name 
202*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET                                   0x00000020
203*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB                                      0
204*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB                                      31
205*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK                                     0xffffffff
206*5113495bSYour Name 
207*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET                                   0x00000024
208*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB                                      0
209*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB                                      31
210*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK                                     0xffffffff
211*5113495bSYour Name 
212*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET                                   0x00000028
213*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB                                      0
214*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB                                      31
215*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK                                     0xffffffff
216*5113495bSYour Name 
217*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET                                  0x0000002c
218*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB                                     0
219*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB                                     31
220*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK                                    0xffffffff
221*5113495bSYour Name 
222*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET                                  0x00000030
223*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB                                     0
224*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB                                     31
225*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK                                    0xffffffff
226*5113495bSYour Name 
227*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET                                  0x00000034
228*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB                                     0
229*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB                                     31
230*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK                                    0xffffffff
231*5113495bSYour Name 
232*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET                                  0x00000038
233*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB                                     0
234*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB                                     31
235*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK                                    0xffffffff
236*5113495bSYour Name 
237*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET                                  0x0000003c
238*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB                                     0
239*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB                                     31
240*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK                                    0xffffffff
241*5113495bSYour Name 
242*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET                                  0x00000040
243*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB                                     0
244*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB                                     31
245*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK                                    0xffffffff
246*5113495bSYour Name 
247*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET                                  0x00000044
248*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB                                     0
249*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB                                     31
250*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK                                    0xffffffff
251*5113495bSYour Name 
252*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET                                  0x00000048
253*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB                                     0
254*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB                                     31
255*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK                                    0xffffffff
256*5113495bSYour Name 
257*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET                                  0x0000004c
258*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB                                     0
259*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB                                     31
260*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK                                    0xffffffff
261*5113495bSYour Name 
262*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET                                  0x00000050
263*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB                                     0
264*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB                                     31
265*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK                                    0xffffffff
266*5113495bSYour Name 
267*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET                                  0x00000054
268*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB                                     0
269*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB                                     31
270*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK                                    0xffffffff
271*5113495bSYour Name 
272*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET                                  0x00000058
273*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB                                     0
274*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB                                     31
275*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK                                    0xffffffff
276*5113495bSYour Name 
277*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET                                  0x0000005c
278*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB                                     0
279*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB                                     31
280*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK                                    0xffffffff
281*5113495bSYour Name 
282*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET                                  0x00000060
283*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB                                     0
284*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB                                     31
285*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK                                    0xffffffff
286*5113495bSYour Name 
287*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET                                  0x00000064
288*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB                                     0
289*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB                                     31
290*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK                                    0xffffffff
291*5113495bSYour Name 
292*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET                                  0x00000068
293*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB                                     0
294*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB                                     27
295*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK                                    0x0fffffff
296*5113495bSYour Name 
297*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET                                 0x00000068
298*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB                                    28
299*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB                                    31
300*5113495bSYour Name #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK                                   0xf0000000
301*5113495bSYour Name 
302*5113495bSYour Name #endif
303