1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 19 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 20 21 #include "uniform_reo_status_header.h" 22 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 27 23 24 struct reo_flush_timeout_list_status { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 uint32_t tlv32_ring_padding : 32; 27 struct uniform_reo_status_header status_header; 28 uint32_t error_detected : 1, 29 timout_list_empty : 1, 30 reserved_2a : 30; 31 uint32_t release_desc_count : 16, 32 forward_buf_count : 16; 33 uint32_t reserved_4a : 32; 34 uint32_t reserved_5a : 32; 35 uint32_t reserved_6a : 32; 36 uint32_t reserved_7a : 32; 37 uint32_t reserved_8a : 32; 38 uint32_t reserved_9a : 32; 39 uint32_t reserved_10a : 32; 40 uint32_t reserved_11a : 32; 41 uint32_t reserved_12a : 32; 42 uint32_t reserved_13a : 32; 43 uint32_t reserved_14a : 32; 44 uint32_t reserved_15a : 32; 45 uint32_t reserved_16a : 32; 46 uint32_t reserved_17a : 32; 47 uint32_t reserved_18a : 32; 48 uint32_t reserved_19a : 32; 49 uint32_t reserved_20a : 32; 50 uint32_t reserved_21a : 32; 51 uint32_t reserved_22a : 32; 52 uint32_t reserved_23a : 32; 53 uint32_t reserved_24a : 32; 54 uint32_t reserved_25a : 28, 55 looping_count : 4; 56 #else 57 uint32_t tlv32_ring_padding : 32; 58 struct uniform_reo_status_header status_header; 59 uint32_t reserved_2a : 30, 60 timout_list_empty : 1, 61 error_detected : 1; 62 uint32_t forward_buf_count : 16, 63 release_desc_count : 16; 64 uint32_t reserved_4a : 32; 65 uint32_t reserved_5a : 32; 66 uint32_t reserved_6a : 32; 67 uint32_t reserved_7a : 32; 68 uint32_t reserved_8a : 32; 69 uint32_t reserved_9a : 32; 70 uint32_t reserved_10a : 32; 71 uint32_t reserved_11a : 32; 72 uint32_t reserved_12a : 32; 73 uint32_t reserved_13a : 32; 74 uint32_t reserved_14a : 32; 75 uint32_t reserved_15a : 32; 76 uint32_t reserved_16a : 32; 77 uint32_t reserved_17a : 32; 78 uint32_t reserved_18a : 32; 79 uint32_t reserved_19a : 32; 80 uint32_t reserved_20a : 32; 81 uint32_t reserved_21a : 32; 82 uint32_t reserved_22a : 32; 83 uint32_t reserved_23a : 32; 84 uint32_t reserved_24a : 32; 85 uint32_t looping_count : 4, 86 reserved_25a : 28; 87 #endif 88 }; 89 90 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 91 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_LSB 0 92 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MSB 31 93 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MASK 0xffffffff 94 95 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 96 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 97 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 98 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff 99 100 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 101 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 102 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 103 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 104 105 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 106 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 107 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 108 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 109 110 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 111 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 112 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 113 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 114 115 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 116 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 117 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 118 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff 119 120 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000c 121 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 122 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 123 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x00000001 124 125 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000c 126 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 127 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 128 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x00000002 129 130 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000c 131 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 132 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 133 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0xfffffffc 134 135 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x00000010 136 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 0 137 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 15 138 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff 139 140 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x00000010 141 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 16 142 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 31 143 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff0000 144 145 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x00000014 146 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 147 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 148 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0xffffffff 149 150 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x00000018 151 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 0 152 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 31 153 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff 154 155 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000001c 156 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 157 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 158 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0xffffffff 159 160 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x00000020 161 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 0 162 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 31 163 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff 164 165 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x00000024 166 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 167 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 168 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0xffffffff 169 170 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x00000028 171 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 0 172 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 31 173 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff 174 175 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000002c 176 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 177 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 178 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0xffffffff 179 180 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x00000030 181 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 0 182 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 31 183 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff 184 185 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x00000034 186 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 187 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 188 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0xffffffff 189 190 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x00000038 191 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 0 192 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 31 193 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff 194 195 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000003c 196 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 197 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 198 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0xffffffff 199 200 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x00000040 201 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 0 202 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 31 203 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff 204 205 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x00000044 206 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 207 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 208 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0xffffffff 209 210 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x00000048 211 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 0 212 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 31 213 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff 214 215 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000004c 216 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 217 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 218 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0xffffffff 219 220 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x00000050 221 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 0 222 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 31 223 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff 224 225 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x00000054 226 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 227 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 228 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0xffffffff 229 230 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x00000058 231 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 0 232 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 31 233 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff 234 235 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000005c 236 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 237 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 238 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0xffffffff 239 240 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x00000060 241 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 0 242 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 31 243 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff 244 245 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x00000064 246 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 247 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 248 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0xffffffff 249 250 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x00000068 251 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 0 252 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 27 253 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff 254 255 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x00000068 256 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 28 257 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 31 258 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf0000000 259 260 #endif 261