xref: /wlan-driver/fw-api/hw/peach/v1/reo_get_queue_stats.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _REO_GET_QUEUE_STATS_H_
19 #define _REO_GET_QUEUE_STATS_H_
20 
21 #include "uniform_reo_cmd_header.h"
22 #define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
23 
24 struct reo_get_queue_stats {
25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
26              struct   uniform_reo_cmd_header                                    cmd_header;
27              uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
28              uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
29                       clear_stats                                             :  1,
30                       reserved_2a                                             : 23;
31              uint32_t reserved_3a                                             : 32;
32              uint32_t reserved_4a                                             : 32;
33              uint32_t reserved_5a                                             : 32;
34              uint32_t reserved_6a                                             : 32;
35              uint32_t reserved_7a                                             : 32;
36              uint32_t reserved_8a                                             : 32;
37 #else
38              struct   uniform_reo_cmd_header                                    cmd_header;
39              uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
40              uint32_t reserved_2a                                             : 23,
41                       clear_stats                                             :  1,
42                       rx_reo_queue_desc_addr_39_32                            :  8;
43              uint32_t reserved_3a                                             : 32;
44              uint32_t reserved_4a                                             : 32;
45              uint32_t reserved_5a                                             : 32;
46              uint32_t reserved_6a                                             : 32;
47              uint32_t reserved_7a                                             : 32;
48              uint32_t reserved_8a                                             : 32;
49 #endif
50 };
51 
52 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET                        0x00000000
53 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB                           0
54 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB                           15
55 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK                          0x0000ffff
56 
57 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                   0x00000000
58 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB                      16
59 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB                      16
60 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK                     0x00010000
61 
62 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET                           0x00000000
63 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB                              17
64 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB                              31
65 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK                             0xfffe0000
66 
67 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                      0x00000004
68 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                         0
69 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                         31
70 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                        0xffffffff
71 
72 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                     0x00000008
73 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                        0
74 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                        7
75 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                       0x000000ff
76 
77 #define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET                                      0x00000008
78 #define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB                                         8
79 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB                                         8
80 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK                                        0x00000100
81 
82 #define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET                                      0x00000008
83 #define REO_GET_QUEUE_STATS_RESERVED_2A_LSB                                         9
84 #define REO_GET_QUEUE_STATS_RESERVED_2A_MSB                                         31
85 #define REO_GET_QUEUE_STATS_RESERVED_2A_MASK                                        0xfffffe00
86 
87 #define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET                                      0x0000000c
88 #define REO_GET_QUEUE_STATS_RESERVED_3A_LSB                                         0
89 #define REO_GET_QUEUE_STATS_RESERVED_3A_MSB                                         31
90 #define REO_GET_QUEUE_STATS_RESERVED_3A_MASK                                        0xffffffff
91 
92 #define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET                                      0x00000010
93 #define REO_GET_QUEUE_STATS_RESERVED_4A_LSB                                         0
94 #define REO_GET_QUEUE_STATS_RESERVED_4A_MSB                                         31
95 #define REO_GET_QUEUE_STATS_RESERVED_4A_MASK                                        0xffffffff
96 
97 #define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET                                      0x00000014
98 #define REO_GET_QUEUE_STATS_RESERVED_5A_LSB                                         0
99 #define REO_GET_QUEUE_STATS_RESERVED_5A_MSB                                         31
100 #define REO_GET_QUEUE_STATS_RESERVED_5A_MASK                                        0xffffffff
101 
102 #define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET                                      0x00000018
103 #define REO_GET_QUEUE_STATS_RESERVED_6A_LSB                                         0
104 #define REO_GET_QUEUE_STATS_RESERVED_6A_MSB                                         31
105 #define REO_GET_QUEUE_STATS_RESERVED_6A_MASK                                        0xffffffff
106 
107 #define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET                                      0x0000001c
108 #define REO_GET_QUEUE_STATS_RESERVED_7A_LSB                                         0
109 #define REO_GET_QUEUE_STATS_RESERVED_7A_MSB                                         31
110 #define REO_GET_QUEUE_STATS_RESERVED_7A_MASK                                        0xffffffff
111 
112 #define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET                                      0x00000020
113 #define REO_GET_QUEUE_STATS_RESERVED_8A_LSB                                         0
114 #define REO_GET_QUEUE_STATS_RESERVED_8A_MSB                                         31
115 #define REO_GET_QUEUE_STATS_RESERVED_8A_MASK                                        0xffffffff
116 
117 #endif
118