1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RESPONSE_END_STATUS_H_ 19 #define _RESPONSE_END_STATUS_H_ 20 21 #include "phytx_abort_request_info.h" 22 #define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 23 24 struct response_end_status { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 uint32_t coex_bt_tx_while_wlan_tx : 1, 27 coex_wan_tx_while_wlan_tx : 1, 28 coex_wlan_tx_while_wlan_tx : 1, 29 global_data_underflow_warning : 1, 30 response_transmit_status : 4, 31 phytx_pkt_end_info_valid : 1, 32 phytx_abort_request_info_valid : 1, 33 generated_response : 3, 34 mba_user_count : 7, 35 mba_fake_bitmap_count : 7, 36 coex_based_tx_bw : 3, 37 trig_response_related : 1, 38 reserved_0a : 1; 39 struct phytx_abort_request_info phytx_abort_request_info_details; 40 uint16_t cbf_segment_request_mask : 8, 41 cbf_segment_sent_mask : 8; 42 uint32_t underflow_mpdu_count : 9, 43 data_underflow_warning : 2, 44 reserved_2b : 10, 45 only_null_delim_sent : 1, 46 brp_info_valid : 1, 47 coex_uwb_tx_while_wlan_tx : 1, 48 coex_lte_tx_while_wlan_tx : 1, 49 reserved_2a : 7; 50 uint32_t mu_response_bitmap_31_0 : 32; 51 uint32_t mu_response_bitmap_36_32 : 5, 52 reserved_4a : 27; 53 uint32_t addr1_31_0 : 32; 54 uint32_t addr1_47_32 : 16, 55 addr2_15_0 : 16; 56 uint32_t addr2_47_16 : 32; 57 uint32_t addr3_31_0 : 32; 58 uint32_t addr3_47_32 : 16, 59 __reserved_g_0005 : 1, 60 secure : 1, 61 __reserved_g_0005_ftm_frame_sent : 1, 62 reserved_20a : 13; 63 #else 64 uint32_t reserved_0a : 1, 65 trig_response_related : 1, 66 coex_based_tx_bw : 3, 67 mba_fake_bitmap_count : 7, 68 mba_user_count : 7, 69 generated_response : 3, 70 phytx_abort_request_info_valid : 1, 71 phytx_pkt_end_info_valid : 1, 72 response_transmit_status : 4, 73 global_data_underflow_warning : 1, 74 coex_wlan_tx_while_wlan_tx : 1, 75 coex_wan_tx_while_wlan_tx : 1, 76 coex_bt_tx_while_wlan_tx : 1; 77 uint32_t cbf_segment_sent_mask : 8, 78 cbf_segment_request_mask : 8; 79 struct phytx_abort_request_info phytx_abort_request_info_details; 80 uint32_t reserved_2a : 7, 81 coex_lte_tx_while_wlan_tx : 1, 82 coex_uwb_tx_while_wlan_tx : 1, 83 brp_info_valid : 1, 84 only_null_delim_sent : 1, 85 reserved_2b : 10, 86 data_underflow_warning : 2, 87 underflow_mpdu_count : 9; 88 uint32_t mu_response_bitmap_31_0 : 32; 89 uint32_t reserved_4a : 27, 90 mu_response_bitmap_36_32 : 5; 91 uint32_t addr1_31_0 : 32; 92 uint32_t addr2_15_0 : 16, 93 addr1_47_32 : 16; 94 uint32_t addr2_47_16 : 32; 95 uint32_t addr3_31_0 : 32; 96 uint32_t reserved_20a : 13, 97 __reserved_g_0005_ftm_frame_sent : 1, 98 secure : 1, 99 __reserved_g_0005 : 1, 100 addr3_47_32 : 16; 101 #endif 102 }; 103 104 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 105 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 106 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 107 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 108 109 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 110 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 111 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 112 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000002 113 114 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 115 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 116 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 117 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000004 118 119 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 120 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 121 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 122 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00000008 123 124 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x00000000 125 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 126 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 127 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x000000f0 128 129 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 130 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 131 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 132 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x00000100 133 134 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 135 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 136 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 137 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000200 138 139 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 140 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 141 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 142 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x00001c00 143 144 #define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x00000000 145 #define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 146 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 147 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x000fe000 148 149 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x00000000 150 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 151 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 152 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x07f00000 153 154 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x00000000 155 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 156 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 157 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x38000000 158 159 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 160 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 161 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 162 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x40000000 163 164 #define RESPONSE_END_STATUS_RESERVED_0A_OFFSET 0x00000000 165 #define RESPONSE_END_STATUS_RESERVED_0A_LSB 31 166 #define RESPONSE_END_STATUS_RESERVED_0A_MSB 31 167 #define RESPONSE_END_STATUS_RESERVED_0A_MASK 0x80000000 168 169 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 170 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 171 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 172 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff 173 174 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 175 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 176 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 177 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 178 179 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 180 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 181 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 182 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 183 184 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000004 185 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 16 186 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 23 187 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff0000 188 189 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000004 190 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 24 191 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 31 192 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff000000 193 194 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000008 195 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 196 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 197 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff 198 199 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x00000008 200 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 201 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 202 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x00000600 203 204 #define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x00000008 205 #define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 206 #define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 207 #define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x001ff800 208 209 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x00000008 210 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 211 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 212 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x00200000 213 214 #define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x00000008 215 #define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 216 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 217 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x00400000 218 219 #define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000008 220 #define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_LSB 23 221 #define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MSB 23 222 #define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00800000 223 224 #define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 225 #define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_LSB 24 226 #define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MSB 24 227 #define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x01000000 228 229 #define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x00000008 230 #define RESPONSE_END_STATUS_RESERVED_2A_LSB 25 231 #define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 232 #define RESPONSE_END_STATUS_RESERVED_2A_MASK 0xfe000000 233 234 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000c 235 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 0 236 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 31 237 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff 238 239 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x00000010 240 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 241 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 242 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x0000001f 243 244 #define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x00000010 245 #define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 246 #define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 247 #define RESPONSE_END_STATUS_RESERVED_4A_MASK 0xffffffe0 248 249 #define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x00000014 250 #define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 251 #define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 252 #define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff 253 254 #define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x00000018 255 #define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 256 #define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 257 #define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff 258 259 #define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x00000018 260 #define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 261 #define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 262 #define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff0000 263 264 #define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000001c 265 #define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 266 #define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 267 #define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff 268 269 #define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x00000020 270 #define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 271 #define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 272 #define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff 273 274 #define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x00000024 275 #define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 276 #define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 277 #define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff 278 279 #define RESPONSE_END_STATUS_SECURE_OFFSET 0x00000024 280 #define RESPONSE_END_STATUS_SECURE_LSB 17 281 #define RESPONSE_END_STATUS_SECURE_MSB 17 282 #define RESPONSE_END_STATUS_SECURE_MASK 0x00020000 283 284 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 285 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 286 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 287 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x00040000 288 289 #define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x00000024 290 #define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 291 #define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 292 #define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff80000 293 294 #endif 295