1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RESPONSE_START_STATUS_H_ 19 #define _RESPONSE_START_STATUS_H_ 20 21 #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 22 23 struct response_start_status { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t generated_response : 3, 26 __reserved_g_0012 : 2, 27 trig_response_related : 1, 28 response_sta_count : 7, 29 reserved : 19; 30 uint32_t phy_ppdu_id : 16, 31 sw_peer_id : 16; 32 #else 33 uint32_t reserved : 19, 34 response_sta_count : 7, 35 trig_response_related : 1, 36 __reserved_g_0012 : 2, 37 generated_response : 3; 38 uint32_t sw_peer_id : 16, 39 phy_ppdu_id : 16; 40 #endif 41 }; 42 43 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 44 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 45 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 46 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007 47 48 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 49 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 50 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 51 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020 52 53 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000 54 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 55 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 56 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0 57 58 #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000 59 #define RESPONSE_START_STATUS_RESERVED_LSB 13 60 #define RESPONSE_START_STATUS_RESERVED_MSB 31 61 #define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000 62 63 #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004 64 #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0 65 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15 66 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff 67 68 #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004 69 #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16 70 #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31 71 #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000 72 73 #endif 74