1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_ATTENTION_H_ 19 #define _RX_ATTENTION_H_ 20 21 #define NUM_OF_DWORDS_RX_ATTENTION 3 22 23 struct rx_attention { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t rxpcu_mpdu_filter_in_category : 2, 26 sw_frame_group_id : 7, 27 reserved_0 : 7, 28 phy_ppdu_id : 16; 29 uint32_t first_mpdu : 1, 30 reserved_1a : 1, 31 mcast_bcast : 1, 32 ast_index_not_found : 1, 33 ast_index_timeout : 1, 34 power_mgmt : 1, 35 non_qos : 1, 36 null_data : 1, 37 mgmt_type : 1, 38 ctrl_type : 1, 39 more_data : 1, 40 eosp : 1, 41 a_msdu_error : 1, 42 fragment_flag : 1, 43 order : 1, 44 cce_match : 1, 45 overflow_err : 1, 46 msdu_length_err : 1, 47 tcp_udp_chksum_fail : 1, 48 ip_chksum_fail : 1, 49 sa_idx_invalid : 1, 50 da_idx_invalid : 1, 51 reserved_1b : 1, 52 rx_in_tx_decrypt_byp : 1, 53 encrypt_required : 1, 54 directed : 1, 55 buffer_fragment : 1, 56 mpdu_length_err : 1, 57 tkip_mic_err : 1, 58 decrypt_err : 1, 59 unencrypted_frame_err : 1, 60 fcs_err : 1; 61 uint32_t flow_idx_timeout : 1, 62 flow_idx_invalid : 1, 63 wifi_parser_error : 1, 64 amsdu_parser_error : 1, 65 sa_idx_timeout : 1, 66 da_idx_timeout : 1, 67 msdu_limit_error : 1, 68 da_is_valid : 1, 69 da_is_mcbc : 1, 70 sa_is_valid : 1, 71 decrypt_status_code : 3, 72 rx_bitmap_not_updated : 1, 73 reserved_2 : 17, 74 msdu_done : 1; 75 #else 76 uint32_t phy_ppdu_id : 16, 77 reserved_0 : 7, 78 sw_frame_group_id : 7, 79 rxpcu_mpdu_filter_in_category : 2; 80 uint32_t fcs_err : 1, 81 unencrypted_frame_err : 1, 82 decrypt_err : 1, 83 tkip_mic_err : 1, 84 mpdu_length_err : 1, 85 buffer_fragment : 1, 86 directed : 1, 87 encrypt_required : 1, 88 rx_in_tx_decrypt_byp : 1, 89 reserved_1b : 1, 90 da_idx_invalid : 1, 91 sa_idx_invalid : 1, 92 ip_chksum_fail : 1, 93 tcp_udp_chksum_fail : 1, 94 msdu_length_err : 1, 95 overflow_err : 1, 96 cce_match : 1, 97 order : 1, 98 fragment_flag : 1, 99 a_msdu_error : 1, 100 eosp : 1, 101 more_data : 1, 102 ctrl_type : 1, 103 mgmt_type : 1, 104 null_data : 1, 105 non_qos : 1, 106 power_mgmt : 1, 107 ast_index_timeout : 1, 108 ast_index_not_found : 1, 109 mcast_bcast : 1, 110 reserved_1a : 1, 111 first_mpdu : 1; 112 uint32_t msdu_done : 1, 113 reserved_2 : 17, 114 rx_bitmap_not_updated : 1, 115 decrypt_status_code : 3, 116 sa_is_valid : 1, 117 da_is_mcbc : 1, 118 da_is_valid : 1, 119 msdu_limit_error : 1, 120 da_idx_timeout : 1, 121 sa_idx_timeout : 1, 122 amsdu_parser_error : 1, 123 wifi_parser_error : 1, 124 flow_idx_invalid : 1, 125 flow_idx_timeout : 1; 126 #endif 127 }; 128 129 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 130 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 131 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 132 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 133 134 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x00000000 135 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 136 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 137 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x000001fc 138 139 #define RX_ATTENTION_RESERVED_0_OFFSET 0x00000000 140 #define RX_ATTENTION_RESERVED_0_LSB 9 141 #define RX_ATTENTION_RESERVED_0_MSB 15 142 #define RX_ATTENTION_RESERVED_0_MASK 0x0000fe00 143 144 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x00000000 145 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 146 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 147 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0xffff0000 148 149 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x00000004 150 #define RX_ATTENTION_FIRST_MPDU_LSB 0 151 #define RX_ATTENTION_FIRST_MPDU_MSB 0 152 #define RX_ATTENTION_FIRST_MPDU_MASK 0x00000001 153 154 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x00000004 155 #define RX_ATTENTION_RESERVED_1A_LSB 1 156 #define RX_ATTENTION_RESERVED_1A_MSB 1 157 #define RX_ATTENTION_RESERVED_1A_MASK 0x00000002 158 159 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x00000004 160 #define RX_ATTENTION_MCAST_BCAST_LSB 2 161 #define RX_ATTENTION_MCAST_BCAST_MSB 2 162 #define RX_ATTENTION_MCAST_BCAST_MASK 0x00000004 163 164 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 165 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 3 166 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 3 167 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x00000008 168 169 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x00000004 170 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 4 171 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 4 172 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x00000010 173 174 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x00000004 175 #define RX_ATTENTION_POWER_MGMT_LSB 5 176 #define RX_ATTENTION_POWER_MGMT_MSB 5 177 #define RX_ATTENTION_POWER_MGMT_MASK 0x00000020 178 179 #define RX_ATTENTION_NON_QOS_OFFSET 0x00000004 180 #define RX_ATTENTION_NON_QOS_LSB 6 181 #define RX_ATTENTION_NON_QOS_MSB 6 182 #define RX_ATTENTION_NON_QOS_MASK 0x00000040 183 184 #define RX_ATTENTION_NULL_DATA_OFFSET 0x00000004 185 #define RX_ATTENTION_NULL_DATA_LSB 7 186 #define RX_ATTENTION_NULL_DATA_MSB 7 187 #define RX_ATTENTION_NULL_DATA_MASK 0x00000080 188 189 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x00000004 190 #define RX_ATTENTION_MGMT_TYPE_LSB 8 191 #define RX_ATTENTION_MGMT_TYPE_MSB 8 192 #define RX_ATTENTION_MGMT_TYPE_MASK 0x00000100 193 194 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x00000004 195 #define RX_ATTENTION_CTRL_TYPE_LSB 9 196 #define RX_ATTENTION_CTRL_TYPE_MSB 9 197 #define RX_ATTENTION_CTRL_TYPE_MASK 0x00000200 198 199 #define RX_ATTENTION_MORE_DATA_OFFSET 0x00000004 200 #define RX_ATTENTION_MORE_DATA_LSB 10 201 #define RX_ATTENTION_MORE_DATA_MSB 10 202 #define RX_ATTENTION_MORE_DATA_MASK 0x00000400 203 204 #define RX_ATTENTION_EOSP_OFFSET 0x00000004 205 #define RX_ATTENTION_EOSP_LSB 11 206 #define RX_ATTENTION_EOSP_MSB 11 207 #define RX_ATTENTION_EOSP_MASK 0x00000800 208 209 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x00000004 210 #define RX_ATTENTION_A_MSDU_ERROR_LSB 12 211 #define RX_ATTENTION_A_MSDU_ERROR_MSB 12 212 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x00001000 213 214 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x00000004 215 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 13 216 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 13 217 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x00002000 218 219 #define RX_ATTENTION_ORDER_OFFSET 0x00000004 220 #define RX_ATTENTION_ORDER_LSB 14 221 #define RX_ATTENTION_ORDER_MSB 14 222 #define RX_ATTENTION_ORDER_MASK 0x00004000 223 224 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x00000004 225 #define RX_ATTENTION_CCE_MATCH_LSB 15 226 #define RX_ATTENTION_CCE_MATCH_MSB 15 227 #define RX_ATTENTION_CCE_MATCH_MASK 0x00008000 228 229 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x00000004 230 #define RX_ATTENTION_OVERFLOW_ERR_LSB 16 231 #define RX_ATTENTION_OVERFLOW_ERR_MSB 16 232 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x00010000 233 234 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x00000004 235 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 17 236 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 17 237 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x00020000 238 239 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 240 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 18 241 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 18 242 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 243 244 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x00000004 245 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 19 246 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 19 247 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x00080000 248 249 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x00000004 250 #define RX_ATTENTION_SA_IDX_INVALID_LSB 20 251 #define RX_ATTENTION_SA_IDX_INVALID_MSB 20 252 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x00100000 253 254 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x00000004 255 #define RX_ATTENTION_DA_IDX_INVALID_LSB 21 256 #define RX_ATTENTION_DA_IDX_INVALID_MSB 21 257 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x00200000 258 259 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x00000004 260 #define RX_ATTENTION_RESERVED_1B_LSB 22 261 #define RX_ATTENTION_RESERVED_1B_MSB 22 262 #define RX_ATTENTION_RESERVED_1B_MASK 0x00400000 263 264 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 265 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 23 266 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 23 267 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 268 269 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x00000004 270 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 24 271 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 24 272 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x01000000 273 274 #define RX_ATTENTION_DIRECTED_OFFSET 0x00000004 275 #define RX_ATTENTION_DIRECTED_LSB 25 276 #define RX_ATTENTION_DIRECTED_MSB 25 277 #define RX_ATTENTION_DIRECTED_MASK 0x02000000 278 279 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x00000004 280 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 26 281 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 26 282 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x04000000 283 284 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x00000004 285 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 27 286 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 27 287 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x08000000 288 289 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x00000004 290 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 28 291 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 28 292 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x10000000 293 294 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x00000004 295 #define RX_ATTENTION_DECRYPT_ERR_LSB 29 296 #define RX_ATTENTION_DECRYPT_ERR_MSB 29 297 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x20000000 298 299 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 300 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 30 301 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 30 302 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 303 304 #define RX_ATTENTION_FCS_ERR_OFFSET 0x00000004 305 #define RX_ATTENTION_FCS_ERR_LSB 31 306 #define RX_ATTENTION_FCS_ERR_MSB 31 307 #define RX_ATTENTION_FCS_ERR_MASK 0x80000000 308 309 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 310 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 311 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 312 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x00000001 313 314 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x00000008 315 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 316 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 317 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x00000002 318 319 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x00000008 320 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 321 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 322 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x00000004 323 324 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x00000008 325 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 326 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 327 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x00000008 328 329 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x00000008 330 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 331 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 332 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x00000010 333 334 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x00000008 335 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 336 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 337 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x00000020 338 339 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x00000008 340 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 341 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 342 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x00000040 343 344 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x00000008 345 #define RX_ATTENTION_DA_IS_VALID_LSB 7 346 #define RX_ATTENTION_DA_IS_VALID_MSB 7 347 #define RX_ATTENTION_DA_IS_VALID_MASK 0x00000080 348 349 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x00000008 350 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 351 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 352 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x00000100 353 354 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x00000008 355 #define RX_ATTENTION_SA_IS_VALID_LSB 9 356 #define RX_ATTENTION_SA_IS_VALID_MSB 9 357 #define RX_ATTENTION_SA_IS_VALID_MASK 0x00000200 358 359 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x00000008 360 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 361 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 362 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x00001c00 363 364 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 365 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 366 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 367 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 368 369 #define RX_ATTENTION_RESERVED_2_OFFSET 0x00000008 370 #define RX_ATTENTION_RESERVED_2_LSB 14 371 #define RX_ATTENTION_RESERVED_2_MSB 30 372 #define RX_ATTENTION_RESERVED_2_MASK 0x7fffc000 373 374 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x00000008 375 #define RX_ATTENTION_MSDU_DONE_LSB 31 376 #define RX_ATTENTION_MSDU_DONE_MSB 31 377 #define RX_ATTENTION_MSDU_DONE_MASK 0x80000000 378 379 #endif 380