xref: /wlan-driver/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
19 #define _RXPCU_PPDU_END_LAYOUT_INFO_H_
20 
21 #define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
22 
23 struct rxpcu_ppdu_end_layout_info {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t rssi_legacy_offset                                      :  2,
26                       l_sig_a_offset                                          :  6,
27                       l_sig_b_offset                                          :  6,
28                       ht_sig_offset                                           :  6,
29                       vht_sig_a_offset                                        :  6,
30                       repeat_l_sig_a_offset                                   :  6;
31              uint32_t he_sig_a_su_offset                                      :  6,
32                       he_sig_a_mu_dl_offset                                   :  6,
33                       he_sig_a_mu_ul_offset                                   :  6,
34                       generic_u_sig_offset                                    :  6,
35                       rssi_ht_offset                                          :  7,
36                       reserved_1a                                             :  1;
37              uint32_t vht_sig_b_su20_offset                                   :  7,
38                       vht_sig_b_su40_offset                                   :  7,
39                       vht_sig_b_su80_offset                                   :  7,
40                       vht_sig_b_su160_offset                                  :  7,
41                       reserved_2a                                             :  4;
42              uint32_t vht_sig_b_mu20_offset                                   :  7,
43                       vht_sig_b_mu40_offset                                   :  7,
44                       vht_sig_b_mu80_offset                                   :  7,
45                       vht_sig_b_mu160_offset                                  :  7,
46                       reserved_3a                                             :  4;
47              uint32_t he_sig_b1_mu_offset                                     :  7,
48                       he_sig_b2_mu_offset                                     :  7,
49                       he_sig_b2_ofdma_offset                                  :  7,
50                       first_generic_eht_sig_offset                            :  7,
51                       multiple_generic_eht_sig_included                       :  1,
52                       reserved_4a                                             :  3;
53              uint32_t common_user_info_offset                                 :  7,
54                       first_debug_info_offset                                 :  8,
55                       multiple_debug_info_included                            :  1,
56                       first_other_receive_info_offset                         :  8,
57                       multiple_other_receive_info_included                    :  1,
58                       reserved_5a                                             :  7;
59              uint32_t data_done_offset                                        :  8,
60                       generated_cbf_details_offset                            :  8,
61                       pkt_end_part1_offset                                    :  8,
62                       location_offset                                         :  8;
63              uint32_t __reserved_g_0011                                       :  8,
64                       pkt_end_offset                                          :  8,
65                       abort_request_ack_offset                                :  8,
66                       reserved_7a                                             :  8;
67              uint32_t reserved_8a                                             : 32;
68              uint32_t reserved_9a                                             : 32;
69 #else
70              uint32_t repeat_l_sig_a_offset                                   :  6,
71                       vht_sig_a_offset                                        :  6,
72                       ht_sig_offset                                           :  6,
73                       l_sig_b_offset                                          :  6,
74                       l_sig_a_offset                                          :  6,
75                       rssi_legacy_offset                                      :  2;
76              uint32_t reserved_1a                                             :  1,
77                       rssi_ht_offset                                          :  7,
78                       generic_u_sig_offset                                    :  6,
79                       he_sig_a_mu_ul_offset                                   :  6,
80                       he_sig_a_mu_dl_offset                                   :  6,
81                       he_sig_a_su_offset                                      :  6;
82              uint32_t reserved_2a                                             :  4,
83                       vht_sig_b_su160_offset                                  :  7,
84                       vht_sig_b_su80_offset                                   :  7,
85                       vht_sig_b_su40_offset                                   :  7,
86                       vht_sig_b_su20_offset                                   :  7;
87              uint32_t reserved_3a                                             :  4,
88                       vht_sig_b_mu160_offset                                  :  7,
89                       vht_sig_b_mu80_offset                                   :  7,
90                       vht_sig_b_mu40_offset                                   :  7,
91                       vht_sig_b_mu20_offset                                   :  7;
92              uint32_t reserved_4a                                             :  3,
93                       multiple_generic_eht_sig_included                       :  1,
94                       first_generic_eht_sig_offset                            :  7,
95                       he_sig_b2_ofdma_offset                                  :  7,
96                       he_sig_b2_mu_offset                                     :  7,
97                       he_sig_b1_mu_offset                                     :  7;
98              uint32_t reserved_5a                                             :  7,
99                       multiple_other_receive_info_included                    :  1,
100                       first_other_receive_info_offset                         :  8,
101                       multiple_debug_info_included                            :  1,
102                       first_debug_info_offset                                 :  8,
103                       common_user_info_offset                                 :  7;
104              uint32_t location_offset                                         :  8,
105                       pkt_end_part1_offset                                    :  8,
106                       generated_cbf_details_offset                            :  8,
107                       data_done_offset                                        :  8;
108              uint32_t reserved_7a                                             :  8,
109                       abort_request_ack_offset                                :  8,
110                       pkt_end_offset                                          :  8,
111                       __reserved_g_0011                                       :  8;
112              uint32_t reserved_8a                                             : 32;
113              uint32_t reserved_9a                                             : 32;
114 #endif
115 };
116 
117 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET                        0x00000000
118 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB                           0
119 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB                           1
120 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK                          0x00000003
121 
122 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET                            0x00000000
123 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB                               2
124 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB                               7
125 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK                              0x000000fc
126 
127 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET                            0x00000000
128 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB                               8
129 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB                               13
130 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK                              0x00003f00
131 
132 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET                             0x00000000
133 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB                                14
134 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB                                19
135 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK                               0x000fc000
136 
137 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET                          0x00000000
138 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB                             20
139 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB                             25
140 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK                            0x03f00000
141 
142 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET                     0x00000000
143 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB                        26
144 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB                        31
145 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK                       0xfc000000
146 
147 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET                        0x00000004
148 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB                           0
149 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB                           5
150 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK                          0x0000003f
151 
152 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET                     0x00000004
153 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB                        6
154 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB                        11
155 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK                       0x00000fc0
156 
157 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET                     0x00000004
158 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB                        12
159 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB                        17
160 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK                       0x0003f000
161 
162 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET                      0x00000004
163 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB                         18
164 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB                         23
165 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK                        0x00fc0000
166 
167 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET                            0x00000004
168 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB                               24
169 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB                               30
170 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK                              0x7f000000
171 
172 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET                               0x00000004
173 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB                                  31
174 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB                                  31
175 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK                                 0x80000000
176 
177 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET                     0x00000008
178 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB                        0
179 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB                        6
180 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK                       0x0000007f
181 
182 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET                     0x00000008
183 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB                        7
184 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB                        13
185 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK                       0x00003f80
186 
187 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET                     0x00000008
188 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB                        14
189 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB                        20
190 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK                       0x001fc000
191 
192 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET                    0x00000008
193 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB                       21
194 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB                       27
195 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK                      0x0fe00000
196 
197 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET                               0x00000008
198 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB                                  28
199 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB                                  31
200 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK                                 0xf0000000
201 
202 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET                     0x0000000c
203 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB                        0
204 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB                        6
205 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK                       0x0000007f
206 
207 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET                     0x0000000c
208 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB                        7
209 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB                        13
210 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK                       0x00003f80
211 
212 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET                     0x0000000c
213 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB                        14
214 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB                        20
215 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK                       0x001fc000
216 
217 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET                    0x0000000c
218 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB                       21
219 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB                       27
220 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK                      0x0fe00000
221 
222 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET                               0x0000000c
223 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB                                  28
224 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB                                  31
225 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK                                 0xf0000000
226 
227 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET                       0x00000010
228 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB                          0
229 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB                          6
230 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK                         0x0000007f
231 
232 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET                       0x00000010
233 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB                          7
234 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB                          13
235 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK                         0x00003f80
236 
237 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET                    0x00000010
238 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB                       14
239 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB                       20
240 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK                      0x001fc000
241 
242 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET              0x00000010
243 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB                 21
244 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB                 27
245 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK                0x0fe00000
246 
247 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET         0x00000010
248 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB            28
249 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB            28
250 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK           0x10000000
251 
252 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET                               0x00000010
253 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB                                  29
254 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB                                  31
255 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK                                 0xe0000000
256 
257 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET                   0x00000014
258 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB                      0
259 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB                      6
260 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK                     0x0000007f
261 
262 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET                   0x00000014
263 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB                      7
264 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB                      14
265 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK                     0x00007f80
266 
267 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET              0x00000014
268 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB                 15
269 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB                 15
270 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK                0x00008000
271 
272 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET           0x00000014
273 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB              16
274 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB              23
275 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK             0x00ff0000
276 
277 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET      0x00000014
278 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB         24
279 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB         24
280 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK        0x01000000
281 
282 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET                               0x00000014
283 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB                                  25
284 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB                                  31
285 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK                                 0xfe000000
286 
287 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET                          0x00000018
288 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB                             0
289 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB                             7
290 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK                            0x000000ff
291 
292 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET              0x00000018
293 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB                 8
294 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB                 15
295 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK                0x0000ff00
296 
297 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET                      0x00000018
298 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB                         16
299 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB                         23
300 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK                        0x00ff0000
301 
302 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET                           0x00000018
303 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB                              24
304 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB                              31
305 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK                             0xff000000
306 
307 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET                            0x0000001c
308 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB                               8
309 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB                               15
310 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK                              0x0000ff00
311 
312 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET                  0x0000001c
313 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB                     16
314 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB                     23
315 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK                    0x00ff0000
316 
317 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET                               0x0000001c
318 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB                                  24
319 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB                                  31
320 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK                                 0xff000000
321 
322 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET                               0x00000020
323 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB                                  0
324 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB                                  31
325 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK                                 0xffffffff
326 
327 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET                               0x00000024
328 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB                                  0
329 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB                                  31
330 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK                                 0xffffffff
331 
332 #endif
333