1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _TX_FES_SETUP_H_ 19 #define _TX_FES_SETUP_H_ 20 21 #define NUM_OF_DWORDS_TX_FES_SETUP 10 22 23 struct tx_fes_setup { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t schedule_id : 32; 26 uint32_t fes_in_11ax_trigger_response_config : 1, 27 bo_based_tid_aggregation_limit : 4, 28 __reserved_g_0005 : 1, 29 expect_i2r_lmr : 1, 30 transmit_start_reason : 3, 31 use_alt_power_sr : 1, 32 static_2_pwr_mode_status : 1, 33 obss_srg_opport_transmit_status : 1, 34 srp_based_transmit_status : 1, 35 obss_pd_based_transmit_status : 1, 36 puncture_from_all_allowed_modes : 1, 37 schedule_cmd_ring_id : 5, 38 fes_control_mode : 2, 39 number_of_users : 6, 40 mu_type : 1, 41 ofdma_triggered_response : 1, 42 response_to_response_cmd : 1; 43 uint32_t schedule_try : 4, 44 ndp_frame : 2, 45 txbf : 1, 46 allow_txop_exceed_in_1st_pkt : 1, 47 ignore_bw_available : 1, 48 ignore_tbtt : 1, 49 static_bandwidth : 3, 50 set_txop_duration_all_ones : 1, 51 transmission_contains_mu_rts : 1, 52 bw_restricted_frames_embedded : 1, 53 ast_index : 16; 54 uint32_t cv_id : 8, 55 trigger_resp_txpdu_ppdu_boundary : 2, 56 rxpcu_setup_complete_present : 1, 57 rbo_must_have_data_user_limit : 4, 58 mu_ndp : 1, 59 bf_type : 2, 60 cbf_nc_index_mask : 1, 61 cbf_nc_index : 3, 62 cbf_nr_index_mask : 1, 63 cbf_nr_index : 3, 64 secure___reserved_g_0005_ista : 1, 65 ndpa : 1, 66 wait_sifs : 2, 67 cbf_feedback_type_mask : 1, 68 cbf_feedback_type : 1; 69 uint32_t cbf_sounding_token : 6, 70 cbf_sounding_token_mask : 1, 71 cbf_bw_mask : 1, 72 cbf_bw : 3, 73 use_static_bw : 1, 74 coex_nack_count : 5, 75 sch_tx_burst_ongoing : 1, 76 gen_tqm_update_mpdu_count_tlv : 1, 77 rts_tx_over___reserved_g_0016 : 1, 78 reserved_4a : 3, 79 optimal_bw_retry_count : 4, 80 fes_continuation_ratio_threshold : 5; 81 uint32_t transmit_cca_bitmap : 32; 82 uint32_t tb___reserved_g_0005 : 1, 83 __reserved_g_0005_trigger_subtype : 4, 84 min_cts2self_count : 4, 85 max_cts2self_count : 4, 86 wifi_radar_enable : 1, 87 reserved_6a : 1, 88 wait_for_chksum_done : 1, 89 reserved_6b : 15, 90 enable_hw_qos_null : 1; 91 uint32_t monitor_override_sta_31_0 : 32; 92 uint32_t monitor_override_sta_36_32 : 5, 93 enable_qos_null_switch_for_eosp : 1, 94 reserved_8a : 26; 95 uint32_t fw2sw_info : 32; 96 #else 97 uint32_t schedule_id : 32; 98 uint32_t response_to_response_cmd : 1, 99 ofdma_triggered_response : 1, 100 mu_type : 1, 101 number_of_users : 6, 102 fes_control_mode : 2, 103 schedule_cmd_ring_id : 5, 104 puncture_from_all_allowed_modes : 1, 105 obss_pd_based_transmit_status : 1, 106 srp_based_transmit_status : 1, 107 obss_srg_opport_transmit_status : 1, 108 static_2_pwr_mode_status : 1, 109 use_alt_power_sr : 1, 110 transmit_start_reason : 3, 111 expect_i2r_lmr : 1, 112 __reserved_g_0005 : 1, 113 bo_based_tid_aggregation_limit : 4, 114 fes_in_11ax_trigger_response_config : 1; 115 uint32_t ast_index : 16, 116 bw_restricted_frames_embedded : 1, 117 transmission_contains_mu_rts : 1, 118 set_txop_duration_all_ones : 1, 119 static_bandwidth : 3, 120 ignore_tbtt : 1, 121 ignore_bw_available : 1, 122 allow_txop_exceed_in_1st_pkt : 1, 123 txbf : 1, 124 ndp_frame : 2, 125 schedule_try : 4; 126 uint32_t cbf_feedback_type : 1, 127 cbf_feedback_type_mask : 1, 128 wait_sifs : 2, 129 ndpa : 1, 130 secure___reserved_g_0005_ista : 1, 131 cbf_nr_index : 3, 132 cbf_nr_index_mask : 1, 133 cbf_nc_index : 3, 134 cbf_nc_index_mask : 1, 135 bf_type : 2, 136 mu_ndp : 1, 137 rbo_must_have_data_user_limit : 4, 138 rxpcu_setup_complete_present : 1, 139 trigger_resp_txpdu_ppdu_boundary : 2, 140 cv_id : 8; 141 uint32_t fes_continuation_ratio_threshold : 5, 142 optimal_bw_retry_count : 4, 143 reserved_4a : 3, 144 rts_tx_over___reserved_g_0016 : 1, 145 gen_tqm_update_mpdu_count_tlv : 1, 146 sch_tx_burst_ongoing : 1, 147 coex_nack_count : 5, 148 use_static_bw : 1, 149 cbf_bw : 3, 150 cbf_bw_mask : 1, 151 cbf_sounding_token_mask : 1, 152 cbf_sounding_token : 6; 153 uint32_t transmit_cca_bitmap : 32; 154 uint32_t enable_hw_qos_null : 1, 155 reserved_6b : 15, 156 wait_for_chksum_done : 1, 157 reserved_6a : 1, 158 wifi_radar_enable : 1, 159 max_cts2self_count : 4, 160 min_cts2self_count : 4, 161 __reserved_g_0005_trigger_subtype : 4, 162 tb___reserved_g_0005 : 1; 163 uint32_t monitor_override_sta_31_0 : 32; 164 uint32_t reserved_8a : 26, 165 enable_qos_null_switch_for_eosp : 1, 166 monitor_override_sta_36_32 : 5; 167 uint32_t fw2sw_info : 32; 168 #endif 169 }; 170 171 #define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000 172 #define TX_FES_SETUP_SCHEDULE_ID_LSB 0 173 #define TX_FES_SETUP_SCHEDULE_ID_MSB 31 174 #define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff 175 176 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 177 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0 178 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0 179 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001 180 181 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004 182 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1 183 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4 184 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e 185 186 #define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004 187 #define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6 188 #define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6 189 #define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040 190 191 #define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004 192 #define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7 193 #define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9 194 #define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380 195 196 #define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004 197 #define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10 198 #define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10 199 #define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400 200 201 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004 202 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11 203 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11 204 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800 205 206 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004 207 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12 208 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12 209 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000 210 211 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 212 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13 213 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13 214 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000 215 216 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 217 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14 218 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14 219 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000 220 221 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004 222 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15 223 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15 224 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000 225 226 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 227 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16 228 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20 229 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 230 231 #define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004 232 #define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21 233 #define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22 234 #define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000 235 236 #define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004 237 #define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23 238 #define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28 239 #define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000 240 241 #define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004 242 #define TX_FES_SETUP_MU_TYPE_LSB 29 243 #define TX_FES_SETUP_MU_TYPE_MSB 29 244 #define TX_FES_SETUP_MU_TYPE_MASK 0x20000000 245 246 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004 247 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30 248 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30 249 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000 250 251 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004 252 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31 253 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31 254 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000 255 256 #define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008 257 #define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 258 #define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 259 #define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f 260 261 #define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008 262 #define TX_FES_SETUP_NDP_FRAME_LSB 4 263 #define TX_FES_SETUP_NDP_FRAME_MSB 5 264 #define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030 265 266 #define TX_FES_SETUP_TXBF_OFFSET 0x00000008 267 #define TX_FES_SETUP_TXBF_LSB 6 268 #define TX_FES_SETUP_TXBF_MSB 6 269 #define TX_FES_SETUP_TXBF_MASK 0x00000040 270 271 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008 272 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 273 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 274 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080 275 276 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008 277 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 278 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 279 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100 280 281 #define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008 282 #define TX_FES_SETUP_IGNORE_TBTT_LSB 9 283 #define TX_FES_SETUP_IGNORE_TBTT_MSB 9 284 #define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200 285 286 #define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008 287 #define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 288 #define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 289 #define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00 290 291 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008 292 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 293 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 294 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000 295 296 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008 297 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 298 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 299 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000 300 301 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008 302 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 303 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 304 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000 305 306 #define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008 307 #define TX_FES_SETUP_AST_INDEX_LSB 16 308 #define TX_FES_SETUP_AST_INDEX_MSB 31 309 #define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000 310 311 #define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c 312 #define TX_FES_SETUP_CV_ID_LSB 0 313 #define TX_FES_SETUP_CV_ID_MSB 7 314 #define TX_FES_SETUP_CV_ID_MASK 0x000000ff 315 316 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c 317 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8 318 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9 319 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300 320 321 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c 322 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10 323 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10 324 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400 325 326 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c 327 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11 328 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14 329 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800 330 331 #define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c 332 #define TX_FES_SETUP_MU_NDP_LSB 15 333 #define TX_FES_SETUP_MU_NDP_MSB 15 334 #define TX_FES_SETUP_MU_NDP_MASK 0x00008000 335 336 #define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c 337 #define TX_FES_SETUP_BF_TYPE_LSB 16 338 #define TX_FES_SETUP_BF_TYPE_MSB 17 339 #define TX_FES_SETUP_BF_TYPE_MASK 0x00030000 340 341 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c 342 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18 343 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18 344 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000 345 346 #define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c 347 #define TX_FES_SETUP_CBF_NC_INDEX_LSB 19 348 #define TX_FES_SETUP_CBF_NC_INDEX_MSB 21 349 #define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000 350 351 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c 352 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22 353 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22 354 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000 355 356 #define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c 357 #define TX_FES_SETUP_CBF_NR_INDEX_LSB 23 358 #define TX_FES_SETUP_CBF_NR_INDEX_MSB 25 359 #define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000 360 361 #define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c 362 #define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26 363 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26 364 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000 365 366 #define TX_FES_SETUP_NDPA_OFFSET 0x0000000c 367 #define TX_FES_SETUP_NDPA_LSB 27 368 #define TX_FES_SETUP_NDPA_MSB 27 369 #define TX_FES_SETUP_NDPA_MASK 0x08000000 370 371 #define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c 372 #define TX_FES_SETUP_WAIT_SIFS_LSB 28 373 #define TX_FES_SETUP_WAIT_SIFS_MSB 29 374 #define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000 375 376 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c 377 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30 378 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30 379 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000 380 381 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c 382 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31 383 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31 384 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000 385 386 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010 387 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 388 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 389 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f 390 391 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010 392 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 393 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 394 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040 395 396 #define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010 397 #define TX_FES_SETUP_CBF_BW_MASK_LSB 7 398 #define TX_FES_SETUP_CBF_BW_MASK_MSB 7 399 #define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080 400 401 #define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010 402 #define TX_FES_SETUP_CBF_BW_LSB 8 403 #define TX_FES_SETUP_CBF_BW_MSB 10 404 #define TX_FES_SETUP_CBF_BW_MASK 0x00000700 405 406 #define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010 407 #define TX_FES_SETUP_USE_STATIC_BW_LSB 11 408 #define TX_FES_SETUP_USE_STATIC_BW_MSB 11 409 #define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800 410 411 #define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010 412 #define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 413 #define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 414 #define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000 415 416 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010 417 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 418 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 419 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000 420 421 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010 422 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 423 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 424 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000 425 426 #define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010 427 #define TX_FES_SETUP_RESERVED_4A_LSB 20 428 #define TX_FES_SETUP_RESERVED_4A_MSB 22 429 #define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000 430 431 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010 432 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 433 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 434 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000 435 436 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010 437 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 438 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 439 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000 440 441 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014 442 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0 443 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31 444 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff 445 446 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018 447 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 448 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 449 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e 450 451 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018 452 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 453 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 454 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0 455 456 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018 457 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 458 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 459 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00 460 461 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018 462 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 463 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 464 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000 465 466 #define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018 467 #define TX_FES_SETUP_RESERVED_6A_LSB 14 468 #define TX_FES_SETUP_RESERVED_6A_MSB 14 469 #define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000 470 471 #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018 472 #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 473 #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 474 #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000 475 476 #define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018 477 #define TX_FES_SETUP_RESERVED_6B_LSB 16 478 #define TX_FES_SETUP_RESERVED_6B_MSB 30 479 #define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000 480 481 #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018 482 #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 483 #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 484 #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000 485 486 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c 487 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0 488 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31 489 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff 490 491 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020 492 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 493 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 494 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f 495 496 #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020 497 #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 498 #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 499 #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020 500 501 #define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020 502 #define TX_FES_SETUP_RESERVED_8A_LSB 6 503 #define TX_FES_SETUP_RESERVED_8A_MSB 31 504 #define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0 505 506 #define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024 507 #define TX_FES_SETUP_FW2SW_INFO_LSB 0 508 #define TX_FES_SETUP_FW2SW_INFO_MSB 31 509 #define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff 510 511 #endif 512