1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _TX_QUEUE_EXTENSION_H_ 19 #define _TX_QUEUE_EXTENSION_H_ 20 21 #define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 22 23 struct tx_queue_extension { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t frame_ctl : 16, 26 qos_ctl : 16; 27 uint32_t ampdu_flag : 1, 28 tx_notify_no_htc_override : 1, 29 reserved_1a : 7, 30 checksum_tso_disable_for_frag : 1, 31 key_id : 8, 32 qos_buf_state_overwrite : 1, 33 buf_state_sta_id : 1, 34 buf_state_source : 1, 35 ht_control_overwrite_enable : 1, 36 ht_control_overwrite_source : 4, 37 reserved_1b : 6; 38 uint32_t ul_headroom_insertion_enable : 1, 39 ul_headroom_offset : 5, 40 bqrp_insertion_enable : 1, 41 bqrp_offset : 5, 42 ul_headroom_rsvd_7_6 : 2, 43 bqr_rsvd_9_8 : 2, 44 base_pn_63_48 : 16; 45 uint32_t base_pn_95_64 : 32; 46 uint32_t base_pn_127_96 : 32; 47 uint32_t ht_control_field_bw20 : 32; 48 uint32_t ht_control_field_bw40 : 32; 49 uint32_t ht_control_field_bw80 : 32; 50 uint32_t ht_control_field_bw160 : 32; 51 uint32_t ht_control_overwrite_mask : 32; 52 uint32_t cas_control_info : 8, 53 cas_offset : 5, 54 cas_insertion_enable : 1, 55 reserved_10a : 2, 56 ht_control_overwrite_source_for_srp : 4, 57 ht_control_overwrite_source_for_bsrp : 4, 58 reserved_10b : 6, 59 mpdu_hdr_len_override_en : 1, 60 bar_ssn_overwrite_enable : 1; 61 uint32_t bar_ssn_offset : 12, 62 mpdu_hdr_len_override_val : 9, 63 reserved_11a : 11; 64 uint32_t ht_control_field_bw320 : 32; 65 uint32_t fw2sw_info : 32; 66 #else 67 uint32_t qos_ctl : 16, 68 frame_ctl : 16; 69 uint32_t reserved_1b : 6, 70 ht_control_overwrite_source : 4, 71 ht_control_overwrite_enable : 1, 72 buf_state_source : 1, 73 buf_state_sta_id : 1, 74 qos_buf_state_overwrite : 1, 75 key_id : 8, 76 checksum_tso_disable_for_frag : 1, 77 reserved_1a : 7, 78 tx_notify_no_htc_override : 1, 79 ampdu_flag : 1; 80 uint32_t base_pn_63_48 : 16, 81 bqr_rsvd_9_8 : 2, 82 ul_headroom_rsvd_7_6 : 2, 83 bqrp_offset : 5, 84 bqrp_insertion_enable : 1, 85 ul_headroom_offset : 5, 86 ul_headroom_insertion_enable : 1; 87 uint32_t base_pn_95_64 : 32; 88 uint32_t base_pn_127_96 : 32; 89 uint32_t ht_control_field_bw20 : 32; 90 uint32_t ht_control_field_bw40 : 32; 91 uint32_t ht_control_field_bw80 : 32; 92 uint32_t ht_control_field_bw160 : 32; 93 uint32_t ht_control_overwrite_mask : 32; 94 uint32_t bar_ssn_overwrite_enable : 1, 95 mpdu_hdr_len_override_en : 1, 96 reserved_10b : 6, 97 ht_control_overwrite_source_for_bsrp : 4, 98 ht_control_overwrite_source_for_srp : 4, 99 reserved_10a : 2, 100 cas_insertion_enable : 1, 101 cas_offset : 5, 102 cas_control_info : 8; 103 uint32_t reserved_11a : 11, 104 mpdu_hdr_len_override_val : 9, 105 bar_ssn_offset : 12; 106 uint32_t ht_control_field_bw320 : 32; 107 uint32_t fw2sw_info : 32; 108 #endif 109 }; 110 111 #define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x00000000 112 #define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 113 #define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 114 #define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x0000ffff 115 116 #define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x00000000 117 #define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 118 #define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 119 #define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0xffff0000 120 121 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x00000004 122 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 0 123 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 0 124 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x00000001 125 126 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x00000004 127 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 1 128 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 1 129 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x00000002 130 131 #define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x00000004 132 #define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 2 133 #define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 8 134 #define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc 135 136 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x00000004 137 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 9 138 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 9 139 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x00000200 140 141 #define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x00000004 142 #define TX_QUEUE_EXTENSION_KEY_ID_LSB 10 143 #define TX_QUEUE_EXTENSION_KEY_ID_MSB 17 144 #define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc00 145 146 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x00000004 147 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 18 148 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 18 149 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x00040000 150 151 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x00000004 152 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 19 153 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 19 154 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x00080000 155 156 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x00000004 157 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 20 158 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 20 159 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x00100000 160 161 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x00000004 162 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 21 163 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 21 164 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x00200000 165 166 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x00000004 167 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 22 168 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 25 169 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c00000 170 171 #define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x00000004 172 #define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 26 173 #define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 31 174 #define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc000000 175 176 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x00000008 177 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 178 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 179 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x00000001 180 181 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x00000008 182 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 183 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 184 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x0000003e 185 186 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x00000008 187 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 188 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 189 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x00000040 190 191 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x00000008 192 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 193 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 194 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x00000f80 195 196 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x00000008 197 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 198 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 199 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x00003000 200 201 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x00000008 202 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 203 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 204 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x0000c000 205 206 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x00000008 207 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 208 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 209 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0xffff0000 210 211 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000c 212 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 0 213 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 31 214 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff 215 216 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x00000010 217 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 218 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 219 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0xffffffff 220 221 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x00000014 222 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 0 223 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 31 224 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff 225 226 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x00000018 227 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 228 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 229 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0xffffffff 230 231 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000001c 232 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 0 233 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 31 234 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff 235 236 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x00000020 237 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 238 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 239 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0xffffffff 240 241 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x00000024 242 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 0 243 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 31 244 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff 245 246 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x00000028 247 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 248 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 249 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x000000ff 250 251 #define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x00000028 252 #define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 253 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 254 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x00001f00 255 256 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x00000028 257 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 258 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 259 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x00002000 260 261 #define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x00000028 262 #define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 263 #define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 264 #define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x0000c000 265 266 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x00000028 267 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 268 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 269 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x000f0000 270 271 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x00000028 272 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 273 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 274 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x00f00000 275 276 #define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x00000028 277 #define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 278 #define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 279 #define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x3f000000 280 281 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x00000028 282 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 283 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 284 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x40000000 285 286 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x00000028 287 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 288 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 289 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x80000000 290 291 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000002c 292 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 0 293 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 11 294 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff 295 296 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000002c 297 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 12 298 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 20 299 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff000 300 301 #define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000002c 302 #define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 21 303 #define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 31 304 #define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe00000 305 306 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x00000030 307 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 308 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 309 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0xffffffff 310 311 #define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x00000034 312 #define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 313 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 314 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff 315 316 #endif 317