1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ 19 #define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ 20 21 #define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 22 23 struct tx_raw_or_native_frame_setup { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t fc_to_ds_mask : 1, 26 fc_from_ds_mask : 1, 27 fc_more_frag_mask : 1, 28 fc_retry_mask : 1, 29 fc_pwr_mgt_mask : 1, 30 fc_more_data_mask : 1, 31 fc_prot_frame_mask : 1, 32 fc_order_mask : 1, 33 duration_field_mask : 1, 34 sequence_control_mask : 1, 35 qc_tid_mask : 1, 36 qc_eosp_mask : 1, 37 qc_ack_policy_mask : 1, 38 qc_amsdu_mask : 1, 39 reserved_0a : 1, 40 qc_15to8_mask : 1, 41 iv_mask : 1, 42 fc_to_ds_setting : 1, 43 fc_from_ds_setting : 1, 44 fc_more_frag_setting : 1, 45 fc_retry_setting : 2, 46 fc_pwr_mgt_setting : 1, 47 fc_more_data_setting : 2, 48 fc_prot_frame_setting : 2, 49 fc_order_setting : 1, 50 qc_tid_setting : 4; 51 uint32_t qc_eosp_setting : 2, 52 qc_ack_policy_setting : 2, 53 qc_amsdu_setting : 1, 54 qc_15to8_setting : 8, 55 mlo_addr_override : 1, 56 mlo_ignore_addr3_override : 1, 57 sequence_control_source : 1, 58 fragment_number : 4, 59 sequence_number : 12; 60 #else 61 uint32_t qc_tid_setting : 4, 62 fc_order_setting : 1, 63 fc_prot_frame_setting : 2, 64 fc_more_data_setting : 2, 65 fc_pwr_mgt_setting : 1, 66 fc_retry_setting : 2, 67 fc_more_frag_setting : 1, 68 fc_from_ds_setting : 1, 69 fc_to_ds_setting : 1, 70 iv_mask : 1, 71 qc_15to8_mask : 1, 72 reserved_0a : 1, 73 qc_amsdu_mask : 1, 74 qc_ack_policy_mask : 1, 75 qc_eosp_mask : 1, 76 qc_tid_mask : 1, 77 sequence_control_mask : 1, 78 duration_field_mask : 1, 79 fc_order_mask : 1, 80 fc_prot_frame_mask : 1, 81 fc_more_data_mask : 1, 82 fc_pwr_mgt_mask : 1, 83 fc_retry_mask : 1, 84 fc_more_frag_mask : 1, 85 fc_from_ds_mask : 1, 86 fc_to_ds_mask : 1; 87 uint32_t sequence_number : 12, 88 fragment_number : 4, 89 sequence_control_source : 1, 90 mlo_ignore_addr3_override : 1, 91 mlo_addr_override : 1, 92 qc_15to8_setting : 8, 93 qc_amsdu_setting : 1, 94 qc_ack_policy_setting : 2, 95 qc_eosp_setting : 2; 96 #endif 97 }; 98 99 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x00000000 100 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 101 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 102 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x00000001 103 104 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x00000000 105 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 106 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 107 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x00000002 108 109 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x00000000 110 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 111 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 112 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x00000004 113 114 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x00000000 115 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 116 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 117 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x00000008 118 119 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x00000000 120 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 121 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 122 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x00000010 123 124 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x00000000 125 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 126 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 127 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x00000020 128 129 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x00000000 130 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 131 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 132 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x00000040 133 134 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x00000000 135 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 136 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 137 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x00000080 138 139 #define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x00000000 140 #define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 141 #define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 142 #define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x00000100 143 144 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x00000000 145 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 146 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 147 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x00000200 148 149 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x00000000 150 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 151 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 152 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x00000400 153 154 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x00000000 155 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 156 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 157 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x00000800 158 159 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x00000000 160 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 161 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 162 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x00001000 163 164 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x00000000 165 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 166 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 167 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x00002000 168 169 #define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x00000000 170 #define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 171 #define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 172 #define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x00004000 173 174 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x00000000 175 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 176 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 177 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x00008000 178 179 #define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x00000000 180 #define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 181 #define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 182 #define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x00010000 183 184 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x00000000 185 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 186 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 187 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x00020000 188 189 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x00000000 190 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 191 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 192 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x00040000 193 194 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x00000000 195 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 196 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 197 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x00080000 198 199 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x00000000 200 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 201 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 202 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x00300000 203 204 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x00000000 205 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 206 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 207 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x00400000 208 209 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x00000000 210 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 211 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 212 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x01800000 213 214 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x00000000 215 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 216 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 217 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x06000000 218 219 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x00000000 220 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 221 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 222 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x08000000 223 224 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x00000000 225 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 226 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 227 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0xf0000000 228 229 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x00000004 230 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 0 231 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 1 232 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x00000003 233 234 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x00000004 235 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 2 236 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 3 237 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c 238 239 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x00000004 240 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 4 241 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 4 242 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x00000010 243 244 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x00000004 245 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 5 246 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 12 247 #define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe0 248 249 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x00000004 250 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 13 251 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 13 252 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x00002000 253 254 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x00000004 255 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 14 256 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 14 257 #define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x00004000 258 259 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x00000004 260 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 15 261 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 15 262 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x00008000 263 264 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x00000004 265 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 16 266 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 19 267 #define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f0000 268 269 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x00000004 270 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 20 271 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 31 272 #define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff00000 273 274 #endif 275