1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _WBM2SW_COMPLETION_RING_TX_H_ 19*5113495bSYour Name #define _WBM2SW_COMPLETION_RING_TX_H_ 20*5113495bSYour Name 21*5113495bSYour Name #include "tx_rate_stats_info.h" 22*5113495bSYour Name #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 23*5113495bSYour Name 24*5113495bSYour Name struct wbm2sw_completion_ring_tx { 25*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; 27*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; 28*5113495bSYour Name uint32_t release_source_module : 3, 29*5113495bSYour Name cache_id : 1, 30*5113495bSYour Name reserved_2a : 2, 31*5113495bSYour Name buffer_or_desc_type : 3, 32*5113495bSYour Name return_buffer_manager : 4, 33*5113495bSYour Name tqm_release_reason : 4, 34*5113495bSYour Name rbm_override_valid : 1, 35*5113495bSYour Name sw_buffer_cookie_11_0 : 12, 36*5113495bSYour Name cookie_conversion_status : 1, 37*5113495bSYour Name wbm_internal_error : 1; 38*5113495bSYour Name uint32_t tqm_status_number : 24, 39*5113495bSYour Name transmit_count : 7, 40*5113495bSYour Name sw_release_details_valid : 1; 41*5113495bSYour Name uint32_t ack_frame_rssi : 8, 42*5113495bSYour Name first_msdu : 1, 43*5113495bSYour Name last_msdu : 1, 44*5113495bSYour Name fw_tx_notify_frame : 3, 45*5113495bSYour Name buffer_timestamp : 19; 46*5113495bSYour Name struct tx_rate_stats_info tx_rate_stats; 47*5113495bSYour Name uint32_t sw_peer_id : 16, 48*5113495bSYour Name tid : 4, 49*5113495bSYour Name sw_buffer_cookie_19_12 : 8, 50*5113495bSYour Name looping_count : 4; 51*5113495bSYour Name #else 52*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; 53*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; 54*5113495bSYour Name uint32_t wbm_internal_error : 1, 55*5113495bSYour Name cookie_conversion_status : 1, 56*5113495bSYour Name sw_buffer_cookie_11_0 : 12, 57*5113495bSYour Name rbm_override_valid : 1, 58*5113495bSYour Name tqm_release_reason : 4, 59*5113495bSYour Name return_buffer_manager : 4, 60*5113495bSYour Name buffer_or_desc_type : 3, 61*5113495bSYour Name reserved_2a : 2, 62*5113495bSYour Name cache_id : 1, 63*5113495bSYour Name release_source_module : 3; 64*5113495bSYour Name uint32_t sw_release_details_valid : 1, 65*5113495bSYour Name transmit_count : 7, 66*5113495bSYour Name tqm_status_number : 24; 67*5113495bSYour Name uint32_t buffer_timestamp : 19, 68*5113495bSYour Name fw_tx_notify_frame : 3, 69*5113495bSYour Name last_msdu : 1, 70*5113495bSYour Name first_msdu : 1, 71*5113495bSYour Name ack_frame_rssi : 8; 72*5113495bSYour Name struct tx_rate_stats_info tx_rate_stats; 73*5113495bSYour Name uint32_t looping_count : 4, 74*5113495bSYour Name sw_buffer_cookie_19_12 : 8, 75*5113495bSYour Name tid : 4, 76*5113495bSYour Name sw_peer_id : 16; 77*5113495bSYour Name #endif 78*5113495bSYour Name }; 79*5113495bSYour Name 80*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 81*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 82*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 83*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 84*5113495bSYour Name 85*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 86*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 87*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 88*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 89*5113495bSYour Name 90*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 91*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 92*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 93*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 94*5113495bSYour Name 95*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 96*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 97*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 98*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 99*5113495bSYour Name 100*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 101*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 102*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 103*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 104*5113495bSYour Name 105*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 106*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 107*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 108*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 109*5113495bSYour Name 110*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 111*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 112*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 113*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 114*5113495bSYour Name 115*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 116*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 117*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 118*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 119*5113495bSYour Name 120*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 121*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 122*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 123*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 124*5113495bSYour Name 125*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 126*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 127*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 128*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 129*5113495bSYour Name 130*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 131*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 132*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 133*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 134*5113495bSYour Name 135*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 136*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 137*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 138*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 139*5113495bSYour Name 140*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 141*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 142*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 143*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 144*5113495bSYour Name 145*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 146*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 147*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 148*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 149*5113495bSYour Name 150*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 151*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 152*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 153*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 154*5113495bSYour Name 155*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 156*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 157*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 158*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 159*5113495bSYour Name 160*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 161*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 162*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 163*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 164*5113495bSYour Name 165*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 166*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 167*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 168*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 169*5113495bSYour Name 170*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 171*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 172*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 173*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 174*5113495bSYour Name 175*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 176*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 177*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 178*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 179*5113495bSYour Name 180*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 181*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 182*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 183*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 184*5113495bSYour Name 185*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 186*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 187*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 188*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 189*5113495bSYour Name 190*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 191*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 192*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 193*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 194*5113495bSYour Name 195*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 196*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 197*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 198*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 199*5113495bSYour Name 200*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 201*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 202*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 203*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 204*5113495bSYour Name 205*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 206*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 207*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 208*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 209*5113495bSYour Name 210*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 211*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 212*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 213*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 214*5113495bSYour Name 215*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 216*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 217*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 218*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 219*5113495bSYour Name 220*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 221*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 222*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 223*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 224*5113495bSYour Name 225*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 226*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 227*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 228*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 229*5113495bSYour Name 230*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 231*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 232*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 233*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 234*5113495bSYour Name 235*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 236*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 237*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 238*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff 239*5113495bSYour Name 240*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c 241*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 242*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 243*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 244*5113495bSYour Name 245*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c 246*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 247*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 248*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 249*5113495bSYour Name 250*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 251*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 252*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 253*5113495bSYour Name #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 254*5113495bSYour Name 255*5113495bSYour Name #endif 256