1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _EXPECTED_RESPONSE_H_ 19 #define _EXPECTED_RESPONSE_H_ 20 21 #define NUM_OF_DWORDS_EXPECTED_RESPONSE 5 22 23 struct expected_response { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t tx_ad2_31_0 : 32; 26 uint32_t tx_ad2_47_32 : 16, 27 expected_response_type : 5, 28 response_to_response : 3, 29 su_ba_user_number : 1, 30 response_info_part2_required : 1, 31 transmitted_bssid_check_en : 1, 32 reserved_1 : 5; 33 uint32_t ndp_sta_partial_aid_2_8_0 : 11, 34 reserved_2 : 10, 35 ndp_sta_partial_aid1_8_0 : 11; 36 uint32_t ast_index : 16, 37 capture_ack_ba_sounding : 1, 38 capture_sounding_1str_20mhz : 1, 39 capture_sounding_1str_40mhz : 1, 40 capture_sounding_1str_80mhz : 1, 41 capture_sounding_1str_160mhz : 1, 42 capture_sounding_1str_240mhz : 1, 43 capture_sounding_1str_320mhz : 1, 44 reserved_3a : 9; 45 uint32_t fcs : 9, 46 reserved_4a : 1, 47 crc : 4, 48 scrambler_seed : 7, 49 reserved_4b : 11; 50 #else 51 uint32_t tx_ad2_31_0 : 32; 52 uint32_t reserved_1 : 5, 53 transmitted_bssid_check_en : 1, 54 response_info_part2_required : 1, 55 su_ba_user_number : 1, 56 response_to_response : 3, 57 expected_response_type : 5, 58 tx_ad2_47_32 : 16; 59 uint32_t ndp_sta_partial_aid1_8_0 : 11, 60 reserved_2 : 10, 61 ndp_sta_partial_aid_2_8_0 : 11; 62 uint32_t reserved_3a : 9, 63 capture_sounding_1str_320mhz : 1, 64 capture_sounding_1str_240mhz : 1, 65 capture_sounding_1str_160mhz : 1, 66 capture_sounding_1str_80mhz : 1, 67 capture_sounding_1str_40mhz : 1, 68 capture_sounding_1str_20mhz : 1, 69 capture_ack_ba_sounding : 1, 70 ast_index : 16; 71 uint32_t reserved_4b : 11, 72 scrambler_seed : 7, 73 crc : 4, 74 reserved_4a : 1, 75 fcs : 9; 76 #endif 77 }; 78 79 #define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000 80 #define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 81 #define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 82 #define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff 83 84 #define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004 85 #define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0 86 #define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15 87 #define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff 88 89 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004 90 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16 91 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20 92 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000 93 94 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004 95 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21 96 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23 97 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000 98 99 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004 100 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24 101 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24 102 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000 103 104 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004 105 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25 106 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25 107 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000 108 109 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004 110 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26 111 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26 112 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000 113 114 #define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004 115 #define EXPECTED_RESPONSE_RESERVED_1_LSB 27 116 #define EXPECTED_RESPONSE_RESERVED_1_MSB 31 117 #define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000 118 119 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008 120 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 121 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 122 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff 123 124 #define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008 125 #define EXPECTED_RESPONSE_RESERVED_2_LSB 11 126 #define EXPECTED_RESPONSE_RESERVED_2_MSB 20 127 #define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800 128 129 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008 130 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 131 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 132 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000 133 134 #define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c 135 #define EXPECTED_RESPONSE_AST_INDEX_LSB 0 136 #define EXPECTED_RESPONSE_AST_INDEX_MSB 15 137 #define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff 138 139 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c 140 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16 141 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16 142 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000 143 144 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c 145 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17 146 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17 147 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000 148 149 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c 150 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18 151 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18 152 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000 153 154 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c 155 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19 156 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19 157 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000 158 159 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c 160 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20 161 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20 162 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000 163 164 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c 165 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21 166 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21 167 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000 168 169 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c 170 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22 171 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22 172 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000 173 174 #define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c 175 #define EXPECTED_RESPONSE_RESERVED_3A_LSB 23 176 #define EXPECTED_RESPONSE_RESERVED_3A_MSB 31 177 #define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000 178 179 #define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010 180 #define EXPECTED_RESPONSE_FCS_LSB 0 181 #define EXPECTED_RESPONSE_FCS_MSB 8 182 #define EXPECTED_RESPONSE_FCS_MASK 0x000001ff 183 184 #define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010 185 #define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 186 #define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 187 #define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200 188 189 #define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010 190 #define EXPECTED_RESPONSE_CRC_LSB 10 191 #define EXPECTED_RESPONSE_CRC_MSB 13 192 #define EXPECTED_RESPONSE_CRC_MASK 0x00003c00 193 194 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010 195 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 196 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 197 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000 198 199 #define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010 200 #define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 201 #define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 202 #define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000 203 204 #endif 205