1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _MACTX_PHY_DESC_H_ 19 #define _MACTX_PHY_DESC_H_ 20 21 #define NUM_OF_DWORDS_MACTX_PHY_DESC 4 22 23 struct mactx_phy_desc { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t reserved_0a : 16, 26 bf_type : 2, 27 wait_sifs : 2, 28 dot11b_preamble_type : 1, 29 pkt_type : 4, 30 su_or_mu : 2, 31 mu_type : 1, 32 bandwidth : 3, 33 channel_capture : 1; 34 uint32_t mcs : 4, 35 global_ofdma_mimo_enable : 1, 36 reserved_1a : 1, 37 stbc : 1, 38 dot11ax_su_extended : 1, 39 dot11ax_trigger_frame_embedded : 1, 40 tx_pwr_shared : 8, 41 tx_pwr_unshared : 8, 42 measure_power : 1, 43 tpc_glut_self_cal : 1, 44 back_to_back_transmission_expected : 1, 45 heavy_clip_nss : 3, 46 txbf_per_packet_no_csd_no_walsh : 1; 47 uint32_t ndp : 2, 48 ul_flag : 1, 49 triggered : 1, 50 ap_pkt_bw : 3, 51 ru_position_start : 8, 52 pcu_ppdu_setup_start_reason : 3, 53 tlv_source : 1, 54 reserved_2a : 2, 55 nss : 3, 56 stream_offset : 3, 57 reserved_2b : 2, 58 clpc_enable : 1, 59 mu_ndp : 1, 60 response_expected : 1; 61 uint32_t rx_chain_mask : 8, 62 rx_chain_mask_valid : 1, 63 ant_sel_valid : 1, 64 ant_sel : 1, 65 cp_setting : 2, 66 he_ppdu_subtype : 2, 67 active_channel : 3, 68 generate_phyrx_tx_start_timing : 1, 69 ltf_size : 2, 70 ru_size_updated_v2 : 4, 71 reserved_3c : 1, 72 u_sig_puncture_pattern_encoding : 6; 73 #else 74 uint32_t channel_capture : 1, 75 bandwidth : 3, 76 mu_type : 1, 77 su_or_mu : 2, 78 pkt_type : 4, 79 dot11b_preamble_type : 1, 80 wait_sifs : 2, 81 bf_type : 2, 82 reserved_0a : 16; 83 uint32_t txbf_per_packet_no_csd_no_walsh : 1, 84 heavy_clip_nss : 3, 85 back_to_back_transmission_expected : 1, 86 tpc_glut_self_cal : 1, 87 measure_power : 1, 88 tx_pwr_unshared : 8, 89 tx_pwr_shared : 8, 90 dot11ax_trigger_frame_embedded : 1, 91 dot11ax_su_extended : 1, 92 stbc : 1, 93 reserved_1a : 1, 94 global_ofdma_mimo_enable : 1, 95 mcs : 4; 96 uint32_t response_expected : 1, 97 mu_ndp : 1, 98 clpc_enable : 1, 99 reserved_2b : 2, 100 stream_offset : 3, 101 nss : 3, 102 reserved_2a : 2, 103 tlv_source : 1, 104 pcu_ppdu_setup_start_reason : 3, 105 ru_position_start : 8, 106 ap_pkt_bw : 3, 107 triggered : 1, 108 ul_flag : 1, 109 ndp : 2; 110 uint32_t u_sig_puncture_pattern_encoding : 6, 111 reserved_3c : 1, 112 ru_size_updated_v2 : 4, 113 ltf_size : 2, 114 generate_phyrx_tx_start_timing : 1, 115 active_channel : 3, 116 he_ppdu_subtype : 2, 117 cp_setting : 2, 118 ant_sel : 1, 119 ant_sel_valid : 1, 120 rx_chain_mask_valid : 1, 121 rx_chain_mask : 8; 122 #endif 123 }; 124 125 #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000 126 #define MACTX_PHY_DESC_RESERVED_0A_LSB 0 127 #define MACTX_PHY_DESC_RESERVED_0A_MSB 15 128 #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff 129 130 #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000 131 #define MACTX_PHY_DESC_BF_TYPE_LSB 16 132 #define MACTX_PHY_DESC_BF_TYPE_MSB 17 133 #define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000 134 135 #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000 136 #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 137 #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 138 #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000 139 140 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000 141 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 142 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 143 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000 144 145 #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000 146 #define MACTX_PHY_DESC_PKT_TYPE_LSB 21 147 #define MACTX_PHY_DESC_PKT_TYPE_MSB 24 148 #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000 149 150 #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000 151 #define MACTX_PHY_DESC_SU_OR_MU_LSB 25 152 #define MACTX_PHY_DESC_SU_OR_MU_MSB 26 153 #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000 154 155 #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000 156 #define MACTX_PHY_DESC_MU_TYPE_LSB 27 157 #define MACTX_PHY_DESC_MU_TYPE_MSB 27 158 #define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000 159 160 #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000 161 #define MACTX_PHY_DESC_BANDWIDTH_LSB 28 162 #define MACTX_PHY_DESC_BANDWIDTH_MSB 30 163 #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000 164 165 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000 166 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 167 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 168 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000 169 170 #define MACTX_PHY_DESC_MCS_OFFSET 0x00000004 171 #define MACTX_PHY_DESC_MCS_LSB 0 172 #define MACTX_PHY_DESC_MCS_MSB 3 173 #define MACTX_PHY_DESC_MCS_MASK 0x0000000f 174 175 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004 176 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4 177 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4 178 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010 179 180 #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004 181 #define MACTX_PHY_DESC_RESERVED_1A_LSB 5 182 #define MACTX_PHY_DESC_RESERVED_1A_MSB 5 183 #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020 184 185 #define MACTX_PHY_DESC_STBC_OFFSET 0x00000004 186 #define MACTX_PHY_DESC_STBC_LSB 6 187 #define MACTX_PHY_DESC_STBC_MSB 6 188 #define MACTX_PHY_DESC_STBC_MASK 0x00000040 189 190 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 191 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7 192 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7 193 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080 194 195 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004 196 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8 197 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8 198 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100 199 200 #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004 201 #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9 202 #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16 203 #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00 204 205 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004 206 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17 207 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24 208 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000 209 210 #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004 211 #define MACTX_PHY_DESC_MEASURE_POWER_LSB 25 212 #define MACTX_PHY_DESC_MEASURE_POWER_MSB 25 213 #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000 214 215 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004 216 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26 217 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26 218 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000 219 220 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004 221 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27 222 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27 223 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000 224 225 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004 226 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28 227 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30 228 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000 229 230 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004 231 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31 232 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31 233 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000 234 235 #define MACTX_PHY_DESC_NDP_OFFSET 0x00000008 236 #define MACTX_PHY_DESC_NDP_LSB 0 237 #define MACTX_PHY_DESC_NDP_MSB 1 238 #define MACTX_PHY_DESC_NDP_MASK 0x00000003 239 240 #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008 241 #define MACTX_PHY_DESC_UL_FLAG_LSB 2 242 #define MACTX_PHY_DESC_UL_FLAG_MSB 2 243 #define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004 244 245 #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008 246 #define MACTX_PHY_DESC_TRIGGERED_LSB 3 247 #define MACTX_PHY_DESC_TRIGGERED_MSB 3 248 #define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008 249 250 #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008 251 #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 252 #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 253 #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070 254 255 #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008 256 #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 257 #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 258 #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80 259 260 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008 261 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 262 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 263 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000 264 265 #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008 266 #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 267 #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 268 #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000 269 270 #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008 271 #define MACTX_PHY_DESC_RESERVED_2A_LSB 19 272 #define MACTX_PHY_DESC_RESERVED_2A_MSB 20 273 #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000 274 275 #define MACTX_PHY_DESC_NSS_OFFSET 0x00000008 276 #define MACTX_PHY_DESC_NSS_LSB 21 277 #define MACTX_PHY_DESC_NSS_MSB 23 278 #define MACTX_PHY_DESC_NSS_MASK 0x00e00000 279 280 #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008 281 #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 282 #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 283 #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000 284 285 #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008 286 #define MACTX_PHY_DESC_RESERVED_2B_LSB 27 287 #define MACTX_PHY_DESC_RESERVED_2B_MSB 28 288 #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000 289 290 #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008 291 #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 292 #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 293 #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000 294 295 #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008 296 #define MACTX_PHY_DESC_MU_NDP_LSB 30 297 #define MACTX_PHY_DESC_MU_NDP_MSB 30 298 #define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000 299 300 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008 301 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 302 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 303 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000 304 305 #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c 306 #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0 307 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7 308 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff 309 310 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c 311 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8 312 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8 313 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100 314 315 #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c 316 #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9 317 #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9 318 #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200 319 320 #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c 321 #define MACTX_PHY_DESC_ANT_SEL_LSB 10 322 #define MACTX_PHY_DESC_ANT_SEL_MSB 10 323 #define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400 324 325 #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c 326 #define MACTX_PHY_DESC_CP_SETTING_LSB 11 327 #define MACTX_PHY_DESC_CP_SETTING_MSB 12 328 #define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800 329 330 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c 331 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13 332 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14 333 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000 334 335 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c 336 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15 337 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17 338 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000 339 340 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c 341 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18 342 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18 343 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000 344 345 #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c 346 #define MACTX_PHY_DESC_LTF_SIZE_LSB 19 347 #define MACTX_PHY_DESC_LTF_SIZE_MSB 20 348 #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000 349 350 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c 351 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21 352 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24 353 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000 354 355 #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c 356 #define MACTX_PHY_DESC_RESERVED_3C_LSB 25 357 #define MACTX_PHY_DESC_RESERVED_3C_MSB 25 358 #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000 359 360 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c 361 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 362 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 363 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 364 365 #endif 366